AD7689 internal temperature sensor

Question I would like to know the conversion method of the temperature measurement using the internal temperature sensor in the AD7689. I have measured the folowing data: at -40 (cell) -> C73 at +80 (cel) -> 140C Using ext Vref 4.096, 16 bit data out Can you please tell me the conversion formula? (volts to temp) Answer The AD7689 temp sensor conversions are forced to be single-ended conversions referenced to GND (unipolar) and are therefore straight binary. This temp sensor output is typical (283 mV @ 25 ̊C) and not trimmed to be absolutely accurate and hence not a guaranteed spec and it changes as the temp increases of decreases. For 4.096V reference, the temp sensor output would be - (4.096V/65536)*output code that you read from the ADC and it changes as the temp increases of decreases.

Should VDD and VIO be powered in a specific order in AD7689, given the datasheet allows any order but warns against VIO exceeding VDD?

Answer: Modified the content as below- It's acceptable to power on VIO before VDD; this won't damage the part. AD7682/AD7689 are independent of VIO-VDD sequencing. However, VDD must be powered to enable the ADC. Always refer to the absolute maximum ratings in the datasheet.

AD7689 digital interface timing

Question I double checked with spec that there is no timing graph except some simple text to descrip the modes of "Reading/Writing During Conversion, Fast Hosts " and "Reading/Writing During Acquisition, Any Speed Hosts " Would you tell the details of timing about these 2 modes? Answer This family of ADCs have the data access gated by the end of conversion (EOC), tCONV(max). Data reads and writes (CFG) need to occur from EOC to EOC. Basically if data access is only taking place during conversion, the host is limited to tDATA time which is limited since when conversion starts (CNV rising) internal circuits take over and force data access in this time. They can read right up to tCONV(max) but can have 1 of 2 things happen. 1. Corrupt data as smaller weighted LSBs are sensitive to digital activity. 2. Miss LSBs as the tCONV(max) is covering hot temperatures and slow process material. The actual tCONV(max) can be 100 ns (or more) < spec so new MSB will overwrite whatever bit is on SDO Data access during acquisition is for customers using both slow or fast hosts since the host is controlling CNV and they have as much time as needed for data access. One thing to make certain is to check to make certain they have released material. Discard any X-grade material as these have a different digital interface! For this family, it is always a pipeline of: configure (n+1), acquisition/conversion (n), readback (n-1). This means that for current (n) acquisition /conversion phase, the CFG is for the next (n+1) acquisition and conversion phase and data readback is for the (n-1) conversion that just occurred. CFG and data readback (SDO) occur at the same time with CFG updating on 1st 14 SCK rising and SDO shifts on SCK falling.

Is it possible to turn on the VIO first and then turn on VDD later in the AD7689?

Answer: Yes, it is safe to power on VIO at 1.8V first, followed by VDD at 3.3V a few milliseconds later in the AD7689.As long as you stay within the absolute maximum ratings, this will not damage the device. For more details, please refer to the datasheet (AD7682/7689). Please note that VDD must be powered on in order to activate the ADC.

AD7689 and AD7949 disable internal clock

Question I'm wondering if the internal clocks in these devices are active only for the conversion or if it is possible to disable them using one of the operating modes? Answer There is no internal clock for AD7689 and AD7949. You have to provide an external serial clock and datasheet recommends a discontinuous SCK because the part is selected with CNV low, and SCK activity begins to write a new configuration word and clock out data. So you can disable external clock as per your requirements.

I am going to use the AD7689 in order to digitize 4...20 mA signals and temperature signals from various sensor

Q I am going to use the AD7689 in order to digitize 4...20 mA signals and temperature signals from various sensor. The reference voltage source will be an external 2.5V (AD441BRZ). The inputs will be driven by AD8628 and AD8231. As the positive supply rail is +5V for all amplifiers, Vref can be exceeded but not any further than Vdd. If this happens on one or more inputs, is this going to affect the conversion results of the other analog inputs and will the converter return FFFF for those inputs where Vref is exceeded? A You should have no problems with the AD7689 if the inputs exceed the reference but remain within the power lines. The crosstalk between channels is mostly capacitive and is ≤125 dB at 100 KHz. It will be less at lower frequencies. If the inputs are out of range but within Vdd-Vss the crosstalk will be no worse. However there is one very important precaution when using CMOS multiplexer circuits - any unused signal inputs MUST be grounded or connected to a potential within the range Vdd-Vss. If unused pins are left open-circuit there is a risk of substrate charge injection and degradation of crosstalk performance. This applies to most MUXes and multiplexed ADCs from Analog Devices and any of our competitors. The data sheet explicitly states on page 16 that over-range and under-range inputs return FS and zero codes respectively so you need have no concern about them.

Precision ADCs

Documents AD7689: FAQ

AD7689: FAQ

Q: Is it possible to turn on the VIO first and then turn on VDD later in the AD7689?

Answer: Yes, it is safe to power on VIO at 1.8V first, followed by VDD at 3.3V a few milliseconds later in the AD7689.As long as you stay within the absolute maximum ratings, this will not damage the device. For more details, please refer to the datasheet (AD7682/7689). Please note that VDD must be powered on in order to activate the ADC.

Q: AD7689 and AD7949 disable internal clock

Question I'm wondering if the internal clocks in these devices are active only for the conversion or if it is possible to disable them using one of the operating modes? Answer There is no internal clock for AD7689 and AD7949. You have to provide an external serial clock and datasheet recommends a discontinuous SCK because the part is selected with CNV low, and SCK activity begins to write a new configuration word and clock out data. So you can disable external clock as per your requirements.

Q: I am going to use the AD7689 in order to digitize 4...20 mA signals and temperature signals from various sensor

Q I am going to use the AD7689 in order to digitize 4...20 mA signals and temperature signals from various sensor. The reference voltage source will be an external 2.5V (AD441BRZ). The inputs will be driven by AD8628 and AD8231. As the positive supply rail is +5V for all amplifiers, Vref can be exceeded but not any further than Vdd. If this happens on one or more inputs, is this going to affect the conversion results of the other analog inputs and will the converter return FFFF for those inputs where Vref is exceeded? A You should have no problems with the AD7689 if the inputs exceed the reference but remain within the power lines. The crosstalk between channels is mostly capacitive and is ≤125 dB at 100 KHz. It will be less at lower frequencies. If the inputs are out of range but within Vdd-Vss the crosstalk will be no worse. However there is one very important precaution when using CMOS multiplexer circuits - any unused signal inputs MUST be grounded or connected to a potential within the range Vdd-Vss. If unused pins are left open-circuit there is a risk of substrate charge injection and degradation of crosstalk performance. This applies to most MUXes and multiplexed ADCs from Analog Devices and any of our competitors. The data sheet explicitly states on page 16 that over-range and under-range inputs return FS and zero codes respectively so you need have no concern about them.