How are the differences in the DBx pinouts between the AD7606C‑16 and AD7606C‑18 reflected on their respective evaluation boards, given that the EVAL‑AD7606C18FMCZ and EVAL‑AD7606C16FMCZ share the same schematic and PCB layout?

The EVAL‑AD7606C18FMCZ evaluation board is designed for the AD7606C‑18, while the EVAL‑AD7606C16FMCZ supports the AD7606C‑16. Although both ADCs are pin‑to‑pin compatible, there are important differences in the parallel output DBx (data bus) pin assignments. The exact DBx mappings for each device are provided in their respective datasheet pin‑description tables. Both evaluation boards use the same hardware schematic and PCB layout, meaning the overall board design is shared. However, the hardware labels, particularly the parallel output test‑point labels on connector P1, were originally based on the AD7606C‑16 pinout. Because the AD7606C‑18 has a different DBx pin mapping, the test‑point labels on the EVAL‑AD7606C18FMCZ (P1) must be updated to reflect the correct AD7606C‑18 data‑bus assignments. The correct set of labels for the EVAL‑AD7606C18FMCZ is provided in the attached reference.

float the input of AD7606

Question For AD7606, when the input pin(V1~V8) is float, and V1GND~V8GND is connected to the ground, the digital output is about 6600, and if using multimeter to measure V1-V1GND, the voltage is about 1.8V. Is this normal? Also, if V1 and V1GND are both connected to GND, the ADC result is 0. Answer the input is floating then we cannot predict where the voltage level is at. Floating inputs is not a condition we recommend. If the inputs are unused they should be tied off to GND.

Current consumption on AVdd and Vdrive individually - for power supply dimensioning

Question In the data sheet is just the sum current for AVcc and Vdrive specified. What is their individual value for the normal operation mode (maximum value)? I need this values to dimension the power supplies. Our configuration is the following: We use all eight channels (AD7606). We intend to use oversampling. The internal reference is used and the serial interface is connected. Answer For this configuration Vdrive is expected to draw less than 100uA. A typical value is 40uA, but this depends on the capacitive load on DoutA and DoutB pins, as well as specific Vdrive voltage level. Note that the 100uA number is based on an oversampling case, and therefore the contribution from the Vdrive during the read operation is averaged over a very large period compared to the read duration, and it is also based on a small capacitive load (10pF) on the Dout. So, for example at 2.5V Vdrive, 10pF load, and 32us time between conversions, the Vdrive current would be approximately 100uA. It will scale approximately proportionately with capacitive load and Vdrive voltage, and inversely with time between conversions. Figure 32 in the RevC datasheet shows typical total AVcc current consumption vs oversampling rate. So when oversampling mode is turned on, the AVcc current consumption is typically close to 20mA. For your information, the total AVCC current is shared approximately equally between the four AVCC pins in that mode also, but up to 6mA should be allowed on any individual AVCC pin .

Current consumption on Vdrive and AVcc

Question In the data sheet is just the sum current for AVcc and Vdrive specified. What is their individual value for the normal operation mode (maximum value)? I need this values to dimension the power supplies. Configuration: - all eight channels (AD7606) - oversampling on - internal reference - serial interface is connected Answer For this configuration Vdrive is expected to draw less than 100uA. A typical value is 40uA, but this depends on the capacitive load on DoutA and DoutB pins, as well as specific Vdrive voltage level. Figure 32 in the RevC datasheet shows typical total AVcc current consumption vs oversampling rate. For your reference I am attaching the screenshot below. So when oversampling mode is turned on, the AVcc current consumption is typically close to 20mA. For your information, the total AVCC current is shared approximately equally between the four AVCC pins in that mode also, but up to 6mA should be allowed on any individual AVCC pin .

AD7606 internal reference max. drift

Question I am trying to find the absolute accuracy figures for the AD7606's on-chip 2.5V reference and am having trouble finding this information on the data sheet (Rev.C). In the "DC Accuracy" specifications section only "typical" figures are given for positive/negative full scale errors and drifts when using the internal reference. In the "Reference Input/Output" section the reference output voltage is given as "2.49/2.505V" but again, this is listed in the "typical" column. Is there a specification for the worst-case accuracy and drift of this internal reference ? Would it be possible to ask AD ? We are proceeding with the design based on this part and so would appreciate this info ASAP. Answer PL reviewed the YA data and calculated a spec for the total reference drift and Full scale error drift. The numbers are in no way guaranteed as a maximum specification. They are only a guideline spec for maximum drift noted during YA on a small sample group. Total reference drift 27PPM/˚C Positive/Negative Full scale error drift 21.1PPM/˚C

EVAL-AD7606EDZ Schematic

Question I cannot find the schematic for the EVAL-AD7606EDZ? Answer The schematic EVAL_AD7606_finalPRD.pdf should be included when you install the software. http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad7606/produ cts/EVAL-AD7606/eb.html

AD7606: shutdown and standby mode

Question When work in shutdown mode, output pins are abnormal and DC power is larger than other mode. DB7: high level(5V); BUSY: high; /CS: high; DC Power >100mA. I use HOST to enter shutdown mode before power up AD7606. Answer if you want to use shutdown or standby mode, please firstly use resistors to pull up RANGE and /STBY to VDRIVE. After power up, use HOST I/O to enter the shutdown or standby mode.

AD7606 evaluation board schematic

Question the pin36 and pin 39 decoupling 10UF capacitor polarity is wrong in attached AD7606 evaluation board schematic Answer Please see the attached for the latest released AD7606 tech note.

AD7606 throughput rate

Question The datasheet describes AD7606 as sampling at throughput rates up to 200 kSPS for all channels. It is not clear if this means 200 ksps for each of the 8 channels or if you need to divide the 200 ksps by 8. Answer The core ADC inside the AD7606 is > 1 MSPS so this is shared across all 8 channels. The cycle time to have all 8 channels converted is 5 us (depending on ser/par interface). So it is 200 ksps for each of the 8 channels(You do not need to divide the 200 ksps by 8).

Why do the AD7606 pins in the "Typical Connection Diagram" such as RANGE, /STDBY have resistors and what values should they be?

Question Why do pins RANGE, STBY, REFSEL, SER/PAR have resistors and what values should these resistors have? Answer These pins are all digital input pins and the resistors act as pull-up/pull-down resistors, in order to pull the logic inputs to the required level. A value of 1Kohm should be enough for these resistors.

How does the FRSTDATA operation function for the AD7606C-16 (1 SDO 3-Wire)?

AD7606C-16 Configuration: 1 SDO 3-Wire No. of SCLK 32 LSB CLK out 31 st SCLK rising edge 1 st FRSTDATA CSb falling edge to 16th SCLK falling edge 2 nd FRSTDATA No 2 nd pulse We can see here in Figure 4., every first set of data that will be released for the AD7606B triggers the FRTSDATA pin one time only even though the next set of data will repeat again. This time it has 2 SDO DoutA and DoutB but it doesn’t change the response. Still, the FRSTDATA specifically triggers from CSb falling edge till the 16th SCLK falling edge with 64 pulses of SCLK. As we can see in the orange box, there is no FRSTDATA pulse from the incoming data set even though the next set of data will arrive.

How does the FRSTDATA operation function for the AD7606C-16 (4 SDO 4-Wire)?

AD7606C-16 Configuration: 4 SDO 4-Wire No. of SCLK 32 LSB CLK out 31 st SCLK rising edge 1 st FRSTDATA CSb falling edge to 16th SCLK falling edge 2 nd FRSTDATA No 2 nd pulse We can see here in Figure 3., every first set of data that will be released for the AD7606B triggers the FRTSDATA pin one time only even though the next set of data will repeat again. This time it has 2 SDO DoutA and DoutB but it doesn’t change the response. Still, the FRSTDATA specifically triggers from CSb falling edge till the 16th SCLK falling edge with 64 pulses of SCLK. As we can see in the orange box, there is no FRSTDATA pulse from the incoming data set even though the next set of data will arrive.

How does the FRSTDATA operation function for the AD7606C-16 (2 SDO 4-Wire)?

AD7606C-16 Configuration: 2 SDO 4-Wire No. of SCLK 64 LSB CLK out 63 rd SCLK rising edge 1 st FRSTDATA CSb falling edge to 16th SCLK falling edge 2 nd FRSTDATA 72nd SCLK falling edge to CSb rising edge We can see here in Figure 2. with the same response as the AD7606C-16, every first set of data that will be released for the AD7606C-16 triggers the FRTSDATA pin every time the next cycle or set of data will repeat again. The FRSTDATA specifically triggers from CSb falling edge till the 16th SCLK falling edge with 64 pulses of SCLK. As we can see in the orange box, there is another FRSTDATA pulse from the incoming data set every time the next set of data will arrive specifically on the 72nd SCLK falling edge till CSb rising edge.

How does the FRSTDATA operation function for the AD7606C-16 (1 SDO 4-Wire) ?

AD7606C-16 Configuration: 1 SDO 4-Wire No. of SCLK 128 LSB CLK out 127 th SCLK rising edge 1 st FRSTDATA CSb falling edge to 16th SCLK falling edge 2 nd FRSTDATA 128th SCLK falling edge to CSb rising edge We can see here in Figure 1. with the same response as the AD7606C-16, every first set of data that will be released for the AD7606C-16 triggers the FRTSDATA pin every time the next cycle or set of data will repeat again. The FRSTDATA specifically triggers from CSb falling edge till the 16th SCLK falling edge with 128 pulses of SCLK. As we can see in the orange box, there is another FRSTDATA pulse from the incoming data set every time the next set of data will arrive specifically on the 128th SCLK falling edge till CSb rising edge.

How does the FRSTDATA operation function for the AD7606C-18 (1 SDO 3-Wire)?

AD7606C-18 Configuration: 1 SDO 3-Wire No. of SCLK 32 LSB CLK out 31 st SCLK rising edge 1 st FRSTDATA CSb falling edge to 16th SCLK falling edge 2 nd FRSTDATA No 2 nd pulse We can see here in Figure 4., every first set of data that will be released for the AD7606B triggers the FRTSDATA pin one time only even though the next set of data will repeat again. This time it has 2 SDO DoutA and DoutB but it doesn’t change the response. Still, the FRSTDATA specifically triggers from CSb falling edge till the 16th SCLK falling edge with 64 pulses of SCLK. As we can see in the orange box, there is no FRSTDATA pulse from the incoming data set even though the next set of data will arrive.

How does the FRSTDATA operation function for the AD7606C-18 (4 SDO 4-Wire)?

AD7606C-18 Configuration: 4 SDO 4-Wire No. of SCLK 32 LSB CLK out 31 st SCLK rising edge 1 st FRSTDATA CSb falling edge to 16th SCLK falling edge 2 nd FRSTDATA No 2 nd pulse We can see here in Figure 3., every first set of data that will be released for the AD7606B triggers the FRTSDATA pin one time only even though the next set of data will repeat again. This time it has 2 SDO DoutA and DoutB but it doesn’t change the response. Still, the FRSTDATA specifically triggers from CSb falling edge till the 16th SCLK falling edge with 64 pulses of SCLK. As we can see in the orange box, there is no FRSTDATA pulse from the incoming data set even though the next set of data will arrive.

How does the FRSTDATA operation function for the AD7606C-18(2 SDO 4-Wire)?

AD7606C-18 Configuration: 2 SDO 4-Wire No. of SCLK 72 LSB CLK out 71 th SCLK rising edge 1 st FRSTDATA CSb falling edge to 18th SCLK falling edge 2 nd FRSTDATA 72nd SCLK falling edge to CSb rising edge We can see here in Figure 2., every first set of data that will be released for the AD7606C-18 triggers the FRTSDATA pin every time the next cycle or set of data will repeat again. This time it has 2 SDO DoutA and DoutB but it doesn’t change the response. Still, the FRSTDATA specifically triggers from CSb falling edge till the 18th SCLK falling edge with 72 pulses of SCLK. As we can see in the orange box, there is another FRSTDATA pulse from the incoming data set every time the next set of data will arrive specifically on the 72nd SCLK falling edge till CSb rising edge.

How does the FRSTDATA operation function for the AD7606C-18 (1 SDO 4-Wire) ?

AD7606C-18 Configuration: 1 SDO 4-Wire No. of SCLK 144 LSB CLK out 143 th SCLK rising edge 1 st FRSTDATA CSb falling edge to 18th SCLK falling edge 2 nd FRSTDATA 144th SCLK falling edge to CSb rising edge We can see here in Figure 1., every first set of data that will be released for the AD7606C-18 triggers the FRTSDATA pin every time the next cycle or set of data will repeat again. The FRSTDATA specifically triggers from CSb falling edge till the 18th SCLK falling edge with 144 pulses of SCLK. As we can see in the orange box, there is another FRSTDATA pulse from the incoming data set every time the next set of data will arrive specifically on the 144th SCLK falling edge till CSb rising edge.

If using the AD7606B/C in serial interface mode, can I leave /WR floating?

Even if Parallel Interface is not selected, /WR input should not be floating. Instead, tie it LOW, HIGH or connected to CNVST.

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AD7606C-18 Recommended for New Designs
The AD7606C-18 is an 18-bit, simultaneous sampling, analog-to-digital data acquisition system (DAS) with eight channels. Each channel contains analog input...
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AD7606C-18 on Analog.com

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AD7606C-16 Recommended for New Designs
The AD7606C-16 is a 16-bit, simultaneous sampling, analog-to-digital data acquisition system (DAS) with eight channels. Each channel contains analog input...
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AD7606C-16 on Analog.com