How does the FRSTDATA operation function for the AD7606B (1 SDO 3-Wire) ?

AD7606B Configuration: 1 SDO 3-Wire No. of SCLK 32 LSB CLK out 31 st SCLK rising edge 1 st FRSTDATA CSb falling edge to 16th SCLK falling edge 2 nd FRSTDATA No 2 nd pulse We can see here in Figure 4., every first set of data that will be released for the AD7606B triggers the FRTSDATA pin one time only even though the next set of data will repeat again. This time it has 2 SDO DoutA and DoutB but it doesn’t change the response. Still, the FRSTDATA specifically triggers from CSb falling edge till the 16th SCLK falling edge with 64 pulses of SCLK. As we can see in the orange box, there is no FRSTDATA pulse from the incoming data set even though the next set of data will arrive.

How does the FRSTDATA operation function for the AD7606B (4 SDO 4-Wire) ?

AD7606B Configuration: 4 SDO 4-Wire No. of SCLK 32 LSB CLK out 31 st SCLK rising edge 1 st FRSTDATA CSb falling edge to 16th SCLK falling edge 2 nd FRSTDATA No 2 nd pulse We can see here in Figure 3., every first set of data that will be released for the AD7606B triggers the FRTSDATA pin one time only even though the next set of data will repeat again. This time it has 2 SDO DoutA and DoutB but it doesn’t change the response. Still, the FRSTDATA specifically triggers from CSb falling edge till the 16th SCLK falling edge with 64 pulses of SCLK. As we can see in the orange box, there is no FRSTDATA pulse from the incoming data set even though the next set of data will arrive.

How does the FRSTDATA operation function for the AD7606B (2 SDO 4-Wire) ?

AD7606B Configuration: 2 SDO 4-Wire No. of SCLK 64 LSB CLK out 63rd SCLK rising edge 1 st FRSTDATA CSb falling edge to 16th SCLK falling edge 2 nd FRSTDATA No 2 nd pulse We can see here in Figure 2., every first set of data that will be released for the AD7606B triggers the FRTSDATA pin one time only even though the next set of data will repeat again. This time it has 2 SDO DoutA and DoutB but it doesn’t change the response. Still, the FRSTDATA specifically triggers from CSb falling edge till the 16th SCLK falling edge with 64 pulses of SCLK. As we can see in the orange box, there is no FRSTDATA pulse from the incoming data set even though the next set of data will arrive.

How does the FRSTDATA operation function for the AD7606B (1 SDO 4-Wire) ?

AD7606B Configuration: 1 SDO 4-Wire No. of SCLK 128 LSB CLK out 127 th SCLK rising edge 1 st FRSTDATA CSb falling edge to 16th SCLK falling edge 2 nd FRSTDATA No 2 nd pulse We can see here in Figure 1., every first set of data that will be released for the AD7606B triggers the FRTSDATA pin one time only even though the next set of data will repeat again. The FRSTDATA specifically triggers from CSb falling edge until the 16th SCLK falling edge with 128 pulses. As we can see in the orange box, there is no FRSTDATA pulse from the incoming data set even though the next set of data will arrive.

Can the analog input be applied before the supply is ready?

As per the absolute maximum rating table, as long as the analog input voltage is kept within ±21V and the analog input current below 10mA no damage will be caused to the device. Independent on the device being powered or not.

How many SPI frames do I need in order to read registers?

As per Figure 75 in the datasheet, when a register is pointed in one SPI frame, its content is received on the next frame. So, if reading N registers we will need N+1 SPI frames. WEN b it´s part of the command word, it means “Write Enable”. So, the AD7606x device is alerted the next bits will be R/W (read or write) followed by the register address. For example, if we try to read the CONFIG register, followed by the RANGE_CH1_CH2 register and the ID register, the SPI sequence would look like: In this example all registers are at their default value, and writing 0x0000 on the last frame switches the AD7606B from Register Mode to ADC mode such that the first frame on the following iteration corresponds to the ADC result of CH1 (0x000C) on the captured frame. (Note both V1 and V1GND are floating, not connected to ground)

What’s the difference between the AD7606 and the AD7606B?

Q: What’s the difference between the AD7606 and the AD7606B? The AD7606B is a directly pin replacement for AD7606, with higher input impedance, throughput rate and extended temperature range, see A.N. 1559 for further details on how to migrate from AD7606 design into AD7606B. However, by writing to its memory map, a series of advanced features can be enabled: -system gain/offset/phase calibration, -per channel analog input range selection (including +/-2.5V range), -sensor disconnect detection -additional oversampling ratios -lower Vdrive operation -diagnostics Q: What sort of errors can be detected through AD7606B diagnostic features? The AD7606B diagnostic features can be enabled to detect individually several errors like: -an inadverted reset, -an overvoltage or undervoltage situation, -and spi read/write error, -memory map or rom corruption, -busy line getting stuck In addition, a diagnostic mux, allows to dedicate any channel to measure internal nodes like supplies, reference, LDOS or a temperature sensor Q: What are the benefits of turning oversampling mode on in the AD7606B? By turning on the oversampling mode, the noise performance is improved. AD7606B allows up to 256 oversampling ratio in software mode. Note that the maximum throughput rate scales down with the oversampling ratio, being 800kSPS/OSR. Check the Software model in the AD7606B product page to see how OSR improves noise performance and limits the throughput. Q: I have a series resistor in front of my analog inputs that causes a gain error, how can I calibrate this gain error off with AD7606B? Having a series resistor in front of the ADC leads to having a system gain error. This system gain could be calibrated on the backend, however the AD7606B provides a feature to compensate this error by just programming the resistor value used on the front-end (up to 65kOhm). This gain calibration register reduces the burden of doing this task on the backend, and achieves it more precisely because the it uses the actual, factory trimmed, input impedance on each device. See A.N. 2011 for further details on AD7606B gain calibration feature, and simulate it through the Software model available on the product page. Q: How does the offset or phase calibration work, what range and resolution do they achieve? The offset calibration allows to add or subtract up to 128LSB to the ADC conversion result, in order to compensate for any known offset error on the front end (e.g. external resistor mismatch). The phase calibration feature allows to delay, on any channel, the sampling instant up to 318.75 us, with a resolution of 1.25us. See A.N. 2011 for further details on AD7606B offset and phase calibration feature, and simulate it through the Software model available on the AD7606B product page. Q: What is the sensor disconnect detection feature implemented on AD7606B and how does it work? The sensor disconnect detection, if enabled, alerts automatically when the input signal gets disconnected from the ADC analog inputs. Alternatively, this feature can be used in manual mode. See A.N. 2011 for further details on how each mode works and how the implemented algorithm works. Q: What ADC output code should I expect if the analog input pin is left floating? It is good practice tying to ground any unused analog input pin. However, if the Vx pin is floating while the VxGND is tied to ground, the ADC result will be as per table below. ADC CODE ADC (V) ±10V range 6336 1.93 ±5V range 10769 1.64 ±2.5V range 16474 1.25

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The AD7606B is a 16-bit, simultaneous sampling, analog-to-digital data acquisition system (DAS) with eight channels, each channel containing analog input...
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