AD7484 Ouput drive capability

Question What is the output drive capability of any output on the IC. We are using a number of the same ICs in our circuit on a common data bus. Unused devices are tristated. We need to know the drive capbility of the devices outputs so that we can estimate rise and fall times. We are powering the device from a 3.3Volt supply. The data bus has nine AD7484 devices connected to it feeding a Microsemi PRoAsic3E FPGA with its input configured as 3v3 LVTTL which has a capacitance of 8pF. The total capacitance of the tracks will be 30pF or less. Therefore the AD7484 data line will be driving eight other tri-stated AD7484 data lines and the FPGA input and track capacitance. Answer The NMOS device on the output driver is generally quite strong on our converters and digital outputs are capable of sinking/sourcing a current well above 200uA. Rise time and fall time is typically in range of few ns and gets extended at low Vdrive and high external capacitance/load. But we did not characterize the AD7484 driving high capacitance digital lines. As this is a parallel part and the data rates are not very fast, we expect that the part will hold up to driving up to 100pF. We put a digital buffer on the output of the AD7484 on the eval board, you may consider doing that, too. Please let me ask you the followings : 1. What value of Vdrive are you using 2. What is the load you expect the AD7484 outputs to see 3. What is the external capacitance on the board It would be helpful to know the answers to these questions before we can come back with a more definite answer.

AD7484: Width of Reset pulse

Question After reset of AD7484, when CONVST signal is given by single time, the BUSY is always low. But when it is given a continuous pulse to CONVST pin, it works well. I found out that the problem is the RESET signal provided for the chip is too short to make it work normally. The specifications you provided on datasheet dosen't specify how long it is, when I correct it, all is well. Answer A reset pulse is vital to ensure correct operation of the AD7484. I would believe that this would fix the issue that the customer previously described. It is the edge of the reset signal that is used to reset the internals of the part so the pulse width shouldn't matter too much once it is a reasonable length (>5ns or so) and happens after the power to the device is stable. Since the customer didn't provide us with any plots showing the reset pulse widths before and after the fix, it's difficult to figure out whether it was truly related to the width of the pulse or the position of the pulse with respect to the VDD line becoming stable. I agree that a minimum pulse width should be included in the datasheet though.

I am working on a project and am using an AD7484 14bit SAR ADC. The device is running in connection with a FPGA, and later with a CPLD.

Q I am working on a project and am using an AD7484 14bit SAR ADC. The device is running in connection with a FPGA, and later with a CPLD. In order to minimize the FPGA/CPLD design, I did not configure the 7484, i.e. I did not write any offset value to the offset register, because I did not want to use bidirectional buses in the project. However, digitizing the input results in errors. When the input goes below a certain limit, the digitizing result is not changing continuously (it remains on a constant value although the input voltage changes continuously) down to a certain voltage, and starts a more or less linear operation again on further decreasing input voltage. My questions are now: - Is it always necessary to initialize the 7484, or has the register a reset value? This is not mentioned in the data sheet. - Is it possible that such a behaviour described above results from not initializing the device, or may this have other causes? P.S.: it must be mentioned that we incidentally had linear operation with the device twice after switching the system off and on again, but this is not reproducable. A The AD7484 requires a reset after power on - no other initialization is required. The AD7484 does not have an internal POR circuit and relies on a rising edge on /RESET after power has been established. As background, the AD7484 uses error correcting logic in order to achieve 14 bit no missing code performance and it is critical that this logic is reset to a known state after power on to ensure proper operation. We recommend an ADM809 to drive the /RESET pin. Of course you could drive the /RESET pin from your CPLD. Lack of a RESET signal is the most likely cause for such a large number of consecutive missing codes. If there is a valid RESET signal applied, the next few things to check are the analog input driver (AD8021 is recommended), Reference (AD780), then power supply decoupling and signal grounding. If we get to that stage it would be useful to review a schematic and layout.

AD7484 Minimum Conversion Time

Q Can you tell me the minimum value of tconv for the AD7484 as it is not specified in table 2 of the datasheet? A On the AD7484 (as with many of our parts), the conversion time is clocked internally and we specify the maximum time that the conversion is going to take. The conversion could be faster but this is of no relevance as you have to wait the maximum conversion time before you can clock out results. Also, we don’t normally specify the minimum conversion time.

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AD7484 Production
The AD7484 is a 14-bit, high speed, low power, successive approximation ADC. The part features a parallel interface with throughput rates up to 3 MSPS...
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AD7484 on Analog.com