AD7888: Using two 8 bit reads for the SCLK

Question How I can read ADC ad7888 data, if I use 8-bit SPI data register (microcontroller AVR)? May I read data for two 8-bit cycles? Answer The SCLK for the AD7888 is also used for the internal bit comparisons... In order to avoid capacitor droop, we strongly recommend that the SCLK timing must be fast enough, such that the conversion time is not less than 50usec ( period that CS is low). This would mean that SCLK should be greater than (1/tconvert ) x 16 = 320Khz. Refer to fig 13 of the datasheet, CS should be kept low for the duration of the two 8 bit reads, SCLK should idle high between the two 8 bit reads.

What is the minimum frequency required for for SCLK ? the data sheet specs tell me the maximum fsclk = 2 MHz, but I cannot find a spec for minimum fsclk.

Q 1. What is the minimum frequency required for for SCLK ? the data sheet specs tell me the maximum fsclk = 2 MHz, but I cannot find a spec for minimum fsclk. 2. What secret is behind the minimum spec for SCLK High Pulse width = 0.4 tsclk and for SCLK Low Pulse width = 0.4 tsclk. Why the factor 0.4 ? A 1) The SCLK is also used for the internal bit comparisons. In order to avoid capacitor droop, we recommend that the SCLK timing must be fast enough, such that the conversion time is not less than 50usec. This would mean that SCLK should be greater than (1/tconvert ) x 16 = 320Khz. 2) The 0.4 factor relates to keeping the mark-space ratio above 40%. If you look at footnote 2 in the notes below the Timing Specifications Table you will see it mentions "Mark/Space ratio for the SCLK input is 40/60 to 60/40. See Serial Interface section." The Serial Interface section is on page 13 of the datasheet.

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The AD7888 is a high speed, low power, 12-bit ADC that operates from a single 2.7 V to 5.25 V power supply. The AD7888 is capable of a 125 kSPS throughput...
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AD7888 on Analog.com

Table of Contents

+Documents
+General: FAQ
+AD1139: FAQ
+AD7091R Conversion Result Change
+AD1556: FAQ
+AD1580: FAQ
+AD1582: FAQ
+AD2S1200: FAQ
+AD2S1205: FAQ
+AD2S1210: FAQ
+AD2S75: FAQ
+AD2S80: FAQ
+AD2S80A: FAQ
+AD2S82A: FAQ
+AD2S83: FAQ
+AD2S90: FAQ
+AD2S99: FAQ
+AD4110-1: FAQ
+AD411x: FAQ
+AD5940: FAQ
+AD598: FAQ
+AD650: FAQ
+AD652: FAQ
+AD654: FAQ
+AD7091: FAQ
+AD7091R-X: FAQ
+AD711: FAQ
+AD7124-4: FAQ
+AD7124-8: FAQ
+AD7134: FAQ
+AD713: FAQ
+AD7142: FAQ
+AD7147: FAQ
+AD7148: FAQ
+AD7150: FAQ
+AD7151: FAQ
+AD7175-2: FAQ
+AD7176-2: FAQ
+AD7176: FAQ
+AD717x: FAQ
+AD7190: FAQ
+AD7192: FAQ
+AD7193: FAQ
+AD7195: FAQ
+AD719x: FAQ
+AD7265: FAQ
+AD7266: FAQ
+AD7280: FAQ
+AD7291: FAQ
+AD7298: FAQ
+AD7305: FAQ
+AD7321: FAQ
+AD7323: FAQ
+AD7328: FAQ
+AD7366-5: FAQ
+AD7367: FAQ
+AD736ARZ: FAQ
+AD737: FAQ
+AD738x : FAQ
+AD7398: FAQ
+AD7400A: FAQ
+AD7401: FAQ
+AD7403: FAQ
+AD74111: FAQ
+AD7415: FAQ
+AD7416: FAQ
+AD7417: FAQ
+AD7418: FAQ
+AD7450: FAQ
+AD7475: FAQ
+AD7484: FAQ
+AD7490: FAQ
+AD7492: FAQ
+AD75019: FAQ
+AD7503: FAQ
+AD7541A: FAQ
+AD7546: FAQ
AD7547: FAQ
+AD7568: FAQ
+AD7578: FAQ
+AD7606-4: FAQ
+AD7606: FAQ
+AD7606B: FAQ
+AD7606C: FAQ
+AD7608: FAQ
+AD7616 FAQ
+AD7616-P: FAQ
+AD7621: FAQ
+AD7625: FAQ
+AD7626: FAQ
+AD7631: FAQ
+AD7653: FAQ
+AD7654: FAQ
+AD7655: FAQ
+AD7656: FAQ
+AD7657-1: FAQ
+AD7663: FAQ
+AD7674: FAQ
+AD7675: FAQ
+AD7678: FAQ
+AD7682: FAQ
+AD7683: FAQ
+AD7684: FAQ
+AD7685: FAQ
+AD7688: FAQ
+AD7689: FAQ
+AD7690: FAQ
+AD7691: FAQ
+AD7705: FAQ
+AD7706: FAQ
+AD7707: FAQ
+AD7708: FAQ
+AD7709: FAQ
+AD7710: FAQ
+AD7711A: FAQ
+AD7712: FAQ
+AD7713: FAQ
+AD7714: FAQ
+AD7714YN: FAQ
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+AD7716: FAQ
+AD7718: FAQ
+AD7719: FAQ
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+AD7865 : FAQ
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+AD7879: FAQ
+AD7887: FAQ
-AD7888: FAQ
- AD7888: Using two 8 bit reads for the SCLK
- What is the minimum frequency required for for SCLK ? the data sheet specs tell me the maximum fsclk = 2 MHz, but I cannot find a spec for minimum fsclk.
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