AD7655: REF pins questions

Question There are three reference pins of this chip, which are REF(PIN 37), REFA(PIN 43), REFB(PIN 42). From my view, REFA(PIN 43) and REFB(PIN 42) are used for channel A and channel B respectively and they can be offered with different levels, if so, should REF(PIN 37) be connected? Or if REF(PIN 37) is used, is it means channel A and channel B are using the same reference level offers by REF(PIN 37)? Could you give us a recommended connection of these REFs or do you have EVB schematic for AD7655? For I just have schematic for AD76xx, in which it is hard to tell how to configure these pins of AD7655. Answer The AD7655 requires an external 2.5V reference applied to REF(PIN 37), REFA(PIN 43), REFB(PIN 42). The AD7655 eval board has the S31, S12 and S13 solder links in place that connects the pin 37 (REF = 2.5V) to pin 42 and pin 43 as shown in the AD76xx user guide’s schematic .

AD7655: How many analogue inputs does the EVAL-AD7655EDZ evaluation board have?

Question How many analogue inputs does the EVAL-AD7655EDZ evaluation board have? The generic user guide for AD76XXEDZ shows only two analogue inputs, whereasthe AD7655 ADC has four analogue inputs. Is there a separate user guide for EVAL-AD7655EDZ? Answer The evaluation board that covers the AD7655 only has two analog inputs. There are several AD76xx products that are covered by this evaluation board.The configuration of the board is determined by the link connections to match the desired input range and type of the user. The user most likelycould attach 4 inputs by taking advantage of these link connections, but there are only two SMB connectors on board. There is no user guide specific to the AD7655, The latest revision of the generic user guide is available on the AD7655 product page on:www.analog.com/AD7655

AD7655: Driven significantly below ground

Question I am using an AD7655 in a data aquusition sytem in which the input sriving (aquasition) voltage can go more than 0.3V negative on a regular basis. Page 18 of the AD7655 states that the input clamp diodes can handle up to 120mA. Could you please tell me what the maximum current that can be handled on an occasional basis when the device is powered up is and what the maximum current is on a regular (once every 4mS for 2ms is. It could be that you do not recommend exceeding -0.3V on a regular basis and that the device should not be made to sink regular negative current, if this is the case it makes my interface circuit more complicated. Answer 120mA is the maximum current that can be applied on an occasional basis. This allows you to choose a protection resistor that is not too high, or to rely on the maximum short cct current limitation of a driver op amp to protect the ADC input. What you are referring to is 50%duty cycle at 250Hz going below -0.3V. In this case there is a considerable thermal effect. How serious depends on the amplitude of the signal - how far negative it goes. I would recommend some kind of external limiting which avoids driving the input negative on a regular basis e.g. an inverting op amp with a diode in parallel with the feedback resistor.

channel selection of AD7655

Question the input channel select control A0 can not work properly, that is when A0=0, it will sample INA2 and INB2, not INA1 and INB1. Is it possible? Another problem is that using the A channel and B channel to sample the same voltage (2.5V reference), and the results are not the same, for example: Ax channel ---> Result: 7FD6, Bx channel: --->Result: 807C. Answer The A0 will sample INx1 when LOW and INx2 when HIGH. They must have a mistake on their logic controlling this as we have looked into this in the past. perhaps they have an older datasheet? This was an error on the last revision. There is a difference in the offset and gain errors from CHA and CHB. This is probably what they are observing. The offset error for CHA is in opposite direction of offset error for CHB (one is positive and one is negative). I do notice the 10uF reference decoupling capacitor which is probably not be enough. This should be increased to 22uF or even better 47uF and placed very close to the ADC, preferably right at the REF pin. On the reference itself, the AD1582 is not able to drive the dynamics of the reference. It will require a suitable buffer such as the AD8031 or AD8606 otherwise there will be problems. Or they can just use a good reference such as AD780, ADR421, ADR431 or ADR441.

Question I have a problem witch the AD7655AST. I work in parallel Mode and have a 2,5V ref, all Voltages and Grounds are ok. The IC is full funtion to a Voltage of 0,5V on INA and INB. Over this Voltage the Databits D0 to D5 are allways low. When I change the high and low Byte with the BYTESWAP pin I have the same problem with D8 to D13. Answer Stuck bits are usually indicative of incorrect REF decoupling. The ADC REF input needs a low ESR decoupling cap (we recommend a 47uF in the datasheet) placed right at the REF pin. If you lower the input to something small, the problem probably goes away. A little background as to why this is: During conversion, the internal comparator pulls current from the REF pin while performing the successive approximation. The larger the input on the T/H, the more current is pulled from REF and without sufficient decoupling, the REF bounces. Others possible causes could be incorrect decoupling on any of the supplies. We strongly recommend a multilayer PCB with separate analog and digital GND planes connected together under the ADC.

I have a question to the timing of AD7655 in master-mode. Does the following operational sequence function?

Q I have a question to the timing of AD7655 in master-mode. Does the following operational sequence function? MASTER MODE: In the first run an low-impulse on the CNVST line must take place to start the automatic conversions. 'Start': - wait until BUSY (or EOC) goes high - store the value of the channel A - change A/B - wait until EOC goes high - store the value of the channel B - change A/B Goto 'Start' Only does one impulse on the CNVST line have to take place, to start all other conversions? A In NORMAL mode you need to apply a low going pulse on CONVST\ for EACH conversion in e frequency of CONVST is equal to the conversion frequency. The internal clock inside the AD7655 is only used to take the conversion from start to finish but the user has to start each conversion with a low going pulse. The CONVST\ signal does not need to be a short pulse. It can have a duty cycle of 50%. It is only the falling edge that is important. In IMPULSE mode you only need to apply the first low going edge on CONVST\. If you hold CONVST\ low after that, a new conversion will start each time the BUSY line goes low. This will result in an overall conversion rate of around 888kSPS, but this is subject to quite a wide tolerance since the frequency of the internal clock is not very precise.

Could you tell me if it exist a simple exercise to verfiy the good working of the AD7665. If it exist could you explain me. thank you

Q Could you tell me if it exist a simple exercise to verfiy the good working of the AD7665. If it exist could you explain me. thank you A A quick and easy way to evaluate the AD7665 is to use the AD7665 eval board with the eval control board and software. The software provided with the AD7665 eval board, is for use only with the eval control board. The AD7665 can be used without the control board, using your own software, however the software provided, provides an easy low cost method of evaluating the AD7665. The eval control board is used with a lot of our evaluation ADC systems..AD76XX family…that are low to medium speed ( not for use with the very high speed ADC’s used in the communications market), therefore once you purchase this board, you can use it with an extensive number of our ADC eval boards. If you have already designed in the AD7665 and you find that it is not responding, can you double check that there is no risk of an incorrect power sequence in the system between OVDD and DVDD? Refer to pg 5 of the datasheet. OVDD must not exceed DVDD by more than 0.3Volts. This is one known cause of latch-up or damage to the AD7665 device.

AD7665: Latching on power up

Q We have a module built with using AD7665 and power circuits made exactly as it specified in datasheet on page 13 with DVDD connected to AVDD through 47 ohm resistors and two capacitors – 10nf and 10uF. OVDD is coming from 3V3 switching regulator and delayed by about 100ms from 5V(AVDD) settles. It was working fine until it was powered from DC/DC converter with 5V rise time about 10ms. But when it been connected to 5V through MOSFET switch, which would apply 5V relatively sharp(50us rise time), we found that AD7665 device is latching and beginning to consume excessive power and won’t operate. Voltage on DVDD was dropping to 2.5V, which means that due resistor in series it consumes 50mA, while under normal operation consumption on DVDD was very small and it was matching AVDD even with resistor in series. We also found that if 10uF tantalum capacitor will be removed, it wont happen. For now we have provisional fix where 10uF capacitor is removed and 10nF ceramic capacitor is replaced by 0.47uF ceramic capacitor of the same size(0603). I can see small lose of performance on high frequencies above 2K, where SINAD drops from 87dB to 86dB, but it still within specification. Any explanation why it can happen? A There is a requirement that OVDD does not exceed DVDD by more than 0.3V. Kindly refer to the Poewr Supply section on page 15 of the www.analog.com/AD7665 datasheet.