Question What is the Human Body model ESD voltage rating of AD7683ARMZ?We are going to use this part in medical application. Answer The Human Body model ESD voltage rating of AD7683ARMZ is 1000V.I’d recommend them to use the AD7685 If it’s a new design since there is a path to higher and lower resolutions with better AC and DC specs in thesame package.Feedback: NO

CMRR of AD7683 and AD7684

Question The AD7683 is pseudo differential input and AD7864 is true differential input. It is known that the pseudo differential input structure features less CMRR than true differential input structure. However, in the datasheet, the CMRR spec of the two parts is the same (65dB @ fin=100KHz). And the ADC simplified schematic shown in figure 20 is the same. Does that mean the common mode rejection capability of the two parts are the same? Answer The CMRR is the same since the parts are identical. The difference being at final test, the AD7684 is programmed for a full differential input span.

Question I want to use the AD7683 instead of the 8320 of Burr Brown. The Device dont work correctly. The Data output is for some input voltages always the same. No bit toggled. The Timing will the same as in the Data sheet. Answer AD7683 is a Successive approximation ADC. You may know that a SAR converter converts by a series of bit trials, deciding the value of the MSB D[15], then D[14], D[13], D[12] ... down to D[0]. Internally, each bit of a DAC is set, and the result compared to the Analog input. The result of this comparison determines the bit value. One of the prerequisites for a SAR converter is that the Analog input (and the reference input) remain "constant" for the each bit trial. If you look at figure 20 of the datasheet , you wil see that the the VREF is connected to the internal device constatnly while the Signal inputs are disconnected during the converstion phase. If one of the bits is incorrectly set (e.g. bit 6 is set to a 1 when it should have been a 0, due to a noise spike during that bit trial) then all of the following bits will be set to either all "0" or all "1", to try to reduce the DAC output to the correct value. The sample and hold at the Analog input ensures that the Analog input to the ADC remains constant during the conversion. However, there is no sample and hold at the reference input. Indeed the Vref pin is a dynamic load for the amplifier or reference that is driving the pin - as stated in the datasheet For this reason a Capacitor of 10uF or greater , right at the inputs of the VREF is required to keep the VREF inputs noise free during conversion. So ensure this CAP is there and ensure that a low impedance reference is used for the Vref.