AD7450: Sample rate estimation (10MHz) and reference voltage

Question 1. What sample rate is estimated on the AD7450 on a 10MHz clock (driven by the FPGA limitation)? 2. What is the minimum voltage reference on the part? I read the spec as 0.3V up to VDD on the AD7450A but maybe this can be confirmed for the AD7450 device. Answer 1. A guide on how-to estimate the sampling rate of the AD7450 is given in the Serial Interface section on page 15 of the www.analog.com/AD7450 datasheet. The estimation is based on the following two equations for the throughput rate: (1) troughput rate = t_2 + 12.5 (1/f_sclk) + t_acq (2) t_acq > 2.5 (1/f_sclk) +t_8 + t_quiet with t_8(max) =35ns and f_sclk=10MHz. The quiet time t_quiet is required to be >25ns and the acquisition time t_acq is required to be >200ns, according to the datasheet. With a clock of 10 MHz the acquisition time is >310ns and the requirement is satisfied easily. Consequently, the maximum throughput rate for AD7450 at a 10MHz clock amounts to throughput rate (max) = 636.9kSPS, assuming t_2(min)=10ns. As this is the best possible throughput rate pushing the specifications to the limits, I would suggest to leave some margin and expect throughput rates of 600kSPS and below. 2. The minimum reference voltage for AD7450 amounts to 100mV and can range up to 3.5V for a supply voltage of 5V. For 3V supplies the minimum reference voltage also amounts to 100mV but can range up to just 2.2V. Both reference voltages spans are given in the Notes section below the Specifications table in the www.analog.com/AD7450 datasheet as well as in the Reference section on page 14. For your reference I am attaching the screenshots below. However, in order to achieve datasheet performance as given in the Specifications section, a reference voltage of 2.5V+/-1% or 1.25V+/-1% is required for 5V or 2.5V supplies, respectively.

Our application will be using Vdd= 5V for the AD7450. According to specs:

Q Our application will be using Vdd= 5V for the AD7450. According to specs: "logic-input-voltage-high Vinh=2.4 Vmin" Is this value valid for the entire Vdd range from 2.7 to 5.25V or just for the lowest voltage of Vdd=2.7V? What is max logic-output-high-voltage, given Vdd=5V? Can this voltage exceed 3.6V? (In other words: can the ADC be interfaced directly to 3.3V DSP ports without any buffers?) A You are correct that for logic inputs, the spec is over the entire supply range. For the logic outputs, when operating the AD7450 with a 5V supply, the maximum digital output high voltage is actually VDD. So, unfortunately, it would be be not be possible to directly interface the logic outputs of the AD7450 to a 3.3 V processor. Some extra circuitry will be required; series resistor plus Schottky diode to the 3.3V supply, or level translator chip. The way we solve this problem on our ADCs is by using a separate "Vdrive" pin to power the digital interface. You can see this feature on the AD7490 for example. On the AD7450 we went for small package size and this just wasn't a spare pin for the Vdrive function. The alternative would be to change the AD7450 supply to 3.3V but I am not sure if this is an option.

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AD7450 Production
The AD7450 is a 12-bit, high speed, low power, successive-approximation (SAR) analog-to-digital converter featuring a fully differential analog input....
Datasheet
AD7450 on Analog.com

AD7450A Production
The AD7440Â / AD7450A are 10-bit and 12-bit high speed, low power, successive approximation (SAR) analog-to-digital converters with a fully differential...
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- Our application will be using Vdd= 5V for the AD7450. According to specs:
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