Question Do you have any data for gain drift over time for the AD7799? Answer The gain drift for AD7799 is typically 20ppm/1000 hours.

Question My customer has problems with the SPI interface of the AD7799. When he wants to read out e.g. the status register, he gets as a response two bytes with the value "0". The schematic was checked two times, so we are quite sure that there might be a configuration problem of the SPI interface. Furthermore, is it possible that CS/ is high between two conversions? Answer When the device is powered up and the power supply has settled, 32 1s should be written to the device. This will reset all registers to their default values. When CS is low, you should see the DRDY line pulsing at 16.7Hz. As Brigid-Anne suggested, the customer should then try to read one of the registers. Can you confirm that the customer is writing to the communications register to inform the AD7799 that a read of one of the on-chip registers is being requested. After writing this instruction, the customer should then apply the correct number of SCLK pulses to the part. The register value will be placed on the DOUT line. Is the customer bit-banging a port or is a dedicated serial interface being used. If bit-banging, the customer should check the signals to ensure that the correct number of SCLK pulses is being applied to the AD7799 during the read and write operations. As Brigid-Anne suggested, DIN should be pulled high when it is not being used. Also, SCLK should idle high between read and write operations. Can you also ask the customer to check the SPI pins to ensure that there is no large glitches appearing as the AD7799 may see these as SCLK pulses. There are no known issues with the serial interface. Usually, problems are due to incorrect number of SCLK pulses or noise on the SPI lines. Yes - CS can be taken high between conversion start and data read. After initiating the single conversion, CS can be taken high. The ADC will continue the conversion and return to powerdown mode after the conversion is completed. Since CS is high, the DRDY pin is tri-stated so it will not indicate when the conversion is complete. To initiate a single conversion, code 08 hex is written to the AD7799. This informs the AD7799 that a word is being written to the Mode Register. The value written to the Mode register is 200A hex (A is the update rate). When the conversion is complete, the value 58 hex is written to the AD7799. The customer can then apply 24 SCLK pulses to the AD7799 and the 24-bit conversion is placed on the DOUT line. There is no special power up sequence after power up. The customer should write 32 1s to the device to reset the registers. The user can then configure the part for their application i.e. channel, update rate, gain, etc. However, the power supplies must have powered up and settled and the uC should also have powered up and settled before the 32 1s are written as any 'invalid' data which may be present on the uC's SPI pins during power up may corrupt the AD7799's registers. The on-chip oscillator only takes a few ms to power up and settle. So, can you ask the customer to reset the device after power up and check the DRDY line (CS needs to be low) to see if it is pulsing at 16.7Hz. Check whether a dedicated serial interface is being used or whether bit-banging is being used. Confirm that there is no glitches on the SPI lines which could be causing the problem.

AD7799 AVDD Monitor 1.17V Internal Reference

Question When monitoring a voltage on the AVDD pin, what is the accuracy/stability of the 1.17V internal reference used for analog-digital conversion? Answer For the AVDD monitor, an internal untrimmed 1.17V reference is used. AVDD is divided by 6 and the attenuated voltage is used as the ADC input. Since the internal reference is untrimmed, the conversion which reflects the ADC voltage is not accurate. The AVDD monitor gives a coarse result rather than an accurate result. The error could be as large as 1%.

AD7799: Problems with communications via serial interface

Question I use AD7799 in recommended circuit in continuous conversion mode on 1 channel (1st). Sometimes (perhaps due to EMI) I have some problems with serial interface. recommended way of reset (32 '1') works, but I can't determine the moment, when I must reset device. For example, my device shows 1.0 V (in unipolar mode) and I have some understandable deviation, then suddenly it shows (permanently) 2V or more (with deviation too). Real input voltage is 1.0V, but ADC shows erroneous results. While testing, I recognize, th? error, because I'm sure, that there is exactly 1V. Have I any other ways to recognize, that ADC works erroneously ? All functions are available, serial number (0xX9) is good, but results are bad... What can you recommend here ? Answer The SPI interface is particularly sensitive to noise, here are some recommendations for investigating communications issues: The most likely reason for reading incorrect data from the AD7799 registers is a spurious (extra) clock pulse appearing on the SCLK line. The SPI interface can be particularly sensitive to interfering noise. This can be avoided by careful layout and bypassing, clean power supplies etc (take careful note of recommendation on page 26 of the datasheet) . The time between t1 and t2 can be 0 nSecs min (see timing specs page 8 of datasheet). t1 is the time between CS going low and DOUT/RDY becoming active. Once this time has elapsed, you can begin applying the SCLK pulses. When SCLK goes low, the AD7799 will place the first bit of the 24-bit word on the DOUT pin. You can either latch in the bit when SCLK is low or on the SCLK rising edge. One bit of data is placed on the DOUT pin for each SCLK pulse. We suggest that you should probe the serial interface lines to ensure that the correct number of SCLK pulses are applied to the AD7799. If SCLK can be idled high when it is not being used, this usually simplifies the interface. After CS is taken low, the first SCLK transition will be a high to low transition. At this point you should see the first bit on the DOUT pin. The data can now be read into the FPGA or on the SCLK rising edge. Also, DIN should be idled high when it is not being used. So, after power up, we suggest that you reset the AD7799 by writing 32 1s to the device. Then attempt to read some of the on-chip registers to confirm that the read and write routines are working correctly. If you still cannot read the correct information from the registers, then you will need to verify your code by connecting a scope to SCLK, DIN of the ADC to verify that the correct information is being sent to the ADC as per fig 3 and fig4 on page 7 of the AD7799 datasheet. You could try putting a small value cap from the SCLK pin to AGND. If a capacitor on the SCLK fixes the problem, then it is likely that you have excess noise on your board. The transistors that make up the serial interface are actually quite fast and can react to high frequency noise/interference. Noise - If the SCLK is very noisy and has multiple transitions on each clock edge, then the same data bit will be input or output several times which will cause the ADC and the controller to lose synchronisation. Overshoot/ringing - If the clock edges are very fast, and the SCLK line is quite long then you can get overshoot/ringing, reflections, etc causing false transitions on the line. A little Series resistor may help here.

AD7799: Changing channels

Question Works 100% in a single channel application. Am trying to switch channels on the fly. Will allow me to change channels on initialisation but not during run time? Answer When the channel is changed with this family of products, the ADC is automatically reset. So, the first conversion after a channel change will always be valid. The time for the first conversion after the channel change is 2/Fadc while subsequent conversions will occur at Fadc. Assuming that you are operating the AD7799 in continuous conversion mode, and at the same update rate for each channel, switching channel involves a write to the AD7799 configuration register. The following sequence should be followed: (1).Write 0x0710 to the configuration register to enable AIN1(+) - AIN1(-) in bipolar mode, buffer enabled, at a gain of 128. (2).Continuously read the DRDY pin on the AD7799. When this pin goes low it means that valid data from the enabled channel is available and can be read form the AD7799 data register. (3).Read and record the data from the data register. Repeat steps 2 and 3 until you want to change channel and gain. (4).If you now want to change channel, (to channel 2) write 0x0011 to the configuration register to enable AIN2(+) -AIN2(-), bipolar mode, buffer enabled at a gain of 1. Repeat steps 2 and 3 until you want to change channel and gain. (Go back to step 1)

Cypress USB Code - USB-cy7c68013A

Question I have been checking the support section for this device and although youprovide some basic code to manage device from a microcontroller, there are noinformation regarding to driver/library of USB-cy7c68013A connection port. Please, could you send me source code of evaluation app to customize by myselfor communication library reference to accomplish my R&D stage? Answer We treat the code used by the Cypress part as a canned routine. It was writteninternally. However, we never distribute the code to customers as it would beimpossible to support.

I have a question about the timing of AD7799.

Q I have a question about the timing of AD7799. The Datasheet says "Ready Bit. Cleared when data is written to the data register. Set after the data register is read or after a period of time before the data register is updated with a new conversion result to indicate to the user not to read the conversion data. It is also set when the part is placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data." So I want to know the exactly how much time is that period? And if I check the /RDY pin, it will goes high after a period of time before the data register is updated with a new conversion result, it is the same as /RDY bit, Then how long is this period? In other word, it will tell me how much time left at least for me to read the data. A The DRDY pin goes low when a new conversion is available. If the customer reads the conversion, DRDY will go high as soon as the data register is read. The customer can read the data register even when DRDY is high as it will not be updated until the next conversion is available. If the customer does not read the conversion, then DRDY stays low indicating that a valid conversion is available. However, when the next conversion is available, DRDY goes high when the data register is being updated. DRDY goes high for 0.8 ms approximately. The customer should not read the data register during this period as it will not contain a valid conversion (it will be in a transient state). So, in summary, the customer has a time of 1/Fadc - 0.8 ms typically to read the data register after the DRDY high to low transition occurs (Fadc = update rate selected).