Input pins of AD7124-4

Question Please, could you clear if it is possible use the external reference in AD7124-4 (by pins AIN6 (REFIN2+) and AIN7 (REFIN2-)), And at the same time input differential signal, using AIN5 and AIN7? Answer The pins can operate as analog input (AIN6/AIN7) and as external reference(REFIN2) at the same time.

Where can I find the user guide and schematics for the EVAL-AD7124-4ASDZ evaluation board

A: The user guide and schematics for the EVAL-AD7124-xASDZ are not yet available on the EVAL-AD7124-4ASDZ product page, as they are still in the process of being added. In the meantime, you can access the user guide documentation through the Analog Devices Wiki – AD7124-X User Guide [Analog Devices Wiki] . The schematics can be found on the hardware guide section. We are actively working to link this resource directly on the product page for easier access.

FAQ. When I need multiple analog input channels, should I use multiple AD7124-4/AD7124 or an external MUX?

Answer: For a system that requires multiple channels, one AD7124-8 can support up to 8 differential/15 single ended input channels and one AD7124-4 can support up to 4 differential/7 single ended input channels. If the system requires a greater number of channels, either a single ADC with an external MUX can be used to increase the channel count as shown in Figure 1 or, multiple ADCs can be used (Figure 2). Figure 1. 32 Channels using MUX and single AD7124-8 Figure 1 shows an example for 32 analog input channels using a single AD7124-8. Here, 4 8x1 muxes (ADG707) are connected to 4 of the ADC’s analog input channels, thus supporting 32 differential inputs. The multiplexer logic pins can be controlled via the AD7124-8’s general-purpose output pins. This option simplifies the analog front-end circuitry and digital software interface. However, converting multiple ADC channels will take time. At Full power mode 50/60Hz rejection (FIR 25sps) the throughput time for 32 channels is 41.72ms x 32 = 1.34s . If the system requires faster measurement speed, it is recommended to use multiple AD7124-4/AD7124-8 devices. Figure 2 shows the connections for 4 AD7124-8s which support 32 channels in total. In this mode, the measurement speed will increase by the number of ADCs used. So for the same scenario as above, the throughput time for 32 channels will be reduced to 1.34s/4 = 0.335s . The ADCs can be synchronized so that a common SPI bus can be used by all the ADCs. Synchronisation ensures that the conversions are available from each ADC at the same time, ensuring that all data is captured correctly. For more details please see below threads. FAQ. In AD7124-4/8, Can multiple devices use a common SPI bus since DOUT/RDY are shared? FAQ. How to ensure synchronization of conversion between multiple AD7124-4/AD7124-8 devices? Figure2. 32 Channels using multiple AD7124-8

FAQ. How to ensure synchronization of conversion between multiple AD7124-4/AD7124-8 devices?

Answer: To ensure synchronization between multiple AD7124-4/AD7124-8 devices, the same master clock must be used for all devices. If the AD7124 internal clock has been used, then one ADC serves as the master and uses its own internal clock and this clock is made available on the device CLK pin. This clock is used as the external clock source for other ADCs. To synchronize the sampling instant /SYNC pin can be used to control the start of conversion alternatively a common command such as enabling continuous conversion will reset the conversion process at all parts. It will only have the 1MCLK uncertainty between conversions of different devices.

Is an IBIS model available for the AD7124-4?

Q. Is an IBIS model available for the AD7124-4? A. There is an IBIS model available for the AD7124-4 that can be downloaded at the following link: http://www.analog.com/en/license/ibis-models?mediaPath=media/en/simulation-models/ibis-models/ad7124-4_lfcsp.ibs&modelType=ibis-models

FAQ. In AD7124-4/AD7124-8, Can I use a single AIN pin as analog input pin and shared this pin as output of Internal Excitation Current Source (IOUT) pin?

Answer: Yes, that should work and the number of AIN pins per sensors is minimized. However, sharing pins will add error to the overall conversion as there will be a voltage drop across the R of the RC anti-aliasing filter/EMC filtering which in series with the RTD, thus limited R values can be used. It is recommended for EMC/anti-aliasing optimum performance; it is a good practice to enable IOUT on a dedicated pin and applied to the RTD outside of the AIN input filters. In this case, only leakage current goes through the R value of the external filter so the impact of the R value on overall accuracy is minimize. This implementation uses one extra AIN pin versus the shared implementation.

FAQ. In AD7124-4/AD7124-8, Can I use a single AIN pin as analog input pin and shared this pin as bias voltage (VBIAS) pin to bias the analog input at mid supply?

Answer: Yes, that should work Vbias can be brought out to AIN-. However, if there are large RC values connected to AIN- then AIN+ sees a filtered version of the bias voltage. The difference between the bias voltage at AIN+ and AIN- results in a voltage error that can be detected by the ADC, so it adds an error to the measurements. To use a shared pin approach, limited RC values must be use. To use unlimited RC values, it is recommended to use a dedicated pin for Vbias and applied Vbias as the common mode voltage on the outer side of the anti-aliasing filter.

FAQ. In AD7124-4/AD7124-8 Why DOUT and RDY are shared pin?

Answer: We share the DOUT and RDY pins to reduce the pin count. Sharing DOUT and RDY has some other benefits also. If isolation is used between the ADC and the uC, having a shared DOUT/RDY line reduces the number of isolation channels needed. To know when a conversion is ready, /CS can be taken low and the DOUT/RDY pin can be monitored. Alternatively, the RDY bit in the status register can be monitored.

FAQ. In AD7124-4/AD7124-8, Can multiple devices use a common SPI bus since DOUT/RDY are shared?

Answer: For a system that uses multiple ADCs, the interface can be simplified by synching the devices. For example, configure one ADC as the master and configure the remaining ADCs as slaves. The clock from the master device can then be used as the clock for all parts. Writing a common command to all devices such as selecting continuous conversion mode will reset all ADCs. The customer would then only need to monitor the DRDY signal from the master device. When the master DRDY goes low, read its conversion. At this point, the other ADCs will also have conversions available so their DRDY signals do not need to be monitored. This architecture would simplify the connections between the ADCs and the uC. With this architecture, it is important that all conversions from the ADCs are read back before the next conversion from the master ADC is ready this ensures that all conversions from ADCs are read (ensures no conversions are missed)

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