AD7685: Supplied with VDD, but Vref and Vio removed

Question I use AD7685 with VDD=3.3V and Vref=Vio=1.8V. When I remove power from Vref and Vio but keep VDD at 3.3V: Will this harm the IC in any way? Will there be any voltage's present on SPI pins or will they be pulled hard low? When Vref and Vio power is restored will there be voltage stabilization delays or can I use the part as usual? Answer Removing the voltages from Vref and Vio pins will not damage the part ina any way, but the part won't work without these supplies. Without an applied reference voltage an input signal cannot be applied. Note that the VIO and VDD can be tied together to reduce the number of supplies needed and the AD7685 is independent of power supply sequencing between VIO and VDD. There shouldn’t be any voltage present on SPI if you don’t apply the voltage at VIO pin. The part should work normally when you apply all the required voltages within the datasheet limits.

Max sample size in CN0194

Question We purchased Circuit note 0194 evaluation board and ADI System demonstration platform. I'm satisfied by the product it self but the evaluation software takes too few samples at one time. Could I increase the amount of samples above limited 15000 samples. Or can I connect SDP and CN0194 evaluation board to NI Labview by myself to make a program which is capable to higher samples at one time. Answer We increased the size of the allowable sample size and have uploaded a new version of the software to the FTP site. It can be found at the following URL: ftp://ftp.analog.com/pub/cftl/CN0194/ I do not believe we allow customers to create software for the SDP. If you would like to use your own processor to acquire data, you have access to these signals via test points on the board.

Problem with the AD7685.

Q Problem with the AD7685. The conversion is only on 12 bits. I work in mode 3 wire with no busy indicator. The last 4 LSB bits are always high. I read in hexa 0xXXXF. What are the conditions which may cause this problem. A The ADC needs separate REF decoupling cap placed as close as possible to the REF pin. Keep in mind, this is not a supply decoupling cap; this is part of the REF circuit that we cannot include on the ADC due to the size and value required. Take a look at fig 27 - this cap must be placed as close as possible to the ADC. Inadequate reference decoupling / decoupling too far away from the Ref pin is generally the main reason why our customer's have difficulty getting specified resolution. Here are some additional tips for best performance.: 1. The Ad7685 Ref & Vdd should be reference to the same ground ( ANALOG GND). VIO can be referenced to a digital ground if you wish. 2. You can use one ground plane or two if you want to separate the Digital and analog signals.( which you do ) 3. The ANALOG GND plane should be underneath the AD7685. 4. Fast switching signals ( CONV and CLK) should not be near the ANALOG signal paths and if possible the digital plane should be used to shield the fast switching signals. This will help to reduce the noise/spikes due to switching on the CONV.(like we talked about this morning w.r.t the scope plot) 5. Power supplies should have larger tracks to reduce impedance and also reduce the influence of glitch’s on the ADC. 6. Take note of all coupling considerations for the power supply line and the REF inputs from the datasheet. Use 10uF and 100nF Capacitors for decoupling noisy systems on all lines. .