AD7401: SINC3 filtering

Q We're planning to use the AD7401 with an FPGA for current measurement in a motor control application. The questions concern the post-processing of the modulator output from the AD7401. I've done some reference reading and also implemented the sinc3 filter that is proposed from AD in a computation environment to explore the area, but I don't get the results I expect. My current suspicion is that far more filtering than the sinc3 is required as post processing to receive as outputs of the ADC chain (AD7401+FPGA), sampled data values of the input signal of the isolated modulator. Further, I don't fully trust the verilog sinc3 implementation presented in the data sheet, since the accumulator registers seem to grow beyond their 24 bit numerical range when supplied with an arbitrary pulse train, causing discontinuities to cope with for the following filter stage. (I ran on floating point, so without numeric limitations the output is reasonable, but the information in the signal was nevertheless not what I had expected) Please provide comment on the above. A The code given in the datasheet is what is used in the final test solution for testing the AD7401. They use the Sinc3 filter and this is suitable for guaranteeing datasheet specifications. Higher order filters do not significantly improve performance. The filter is not a 24 bit precision filter. It is only designed to give 16 bit performance. The filter code has internal filter digital buses that are 24 bits and the data out is truncated to 16 bits, all filter coefficients are set to You need this number of bits to guarantee the 16 bit precision, you must drop the last 8 bits. Other filter arrangements are possible and some systems may experience better performance by increasing some of the feedback delays. The filter accuracy is determined by the decimation rate, thus a decimation rate of 256 is required for the 16 bit resolution. If you increase the decimation rate you will have better performance from the AD7401 but this will reduce the throughput of the device and the usable BW. Figure 29 in the datasheet illustrates how increasing the decimation rate effects performance. With the SINC3 filter detailed on the datasheet you should be able to achieve 16 bit performance without any los of data. It is important to remember the filter is for 16 bit resolution not 24 bit resolution. Do you require 24 bit resolution? The accumulator will grow beyond the 24 bits but should not cause any errors, the size of the registers (24-bits) makes sure that the relevant data will not be lost.

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