Question 1

AD7730: Maximum ratings

Accepted Answer

Question I have an AD7730BN part connected to a PC printer port (for develop only) 
 trough a 1K series resistor in SCLK,DIN,DOUT,CS lines. I saw that if I 
 switch-off the AD7730BN power supply I can't start conversion commands but I 
 can read/write to the registers, it seams that the digital section of the part 
 is powered from the data lines. Can be this true?. Some times I found a 
 residual voltage (some mV.) in the analog input pins Can be this due to this 
 phantom power supply? Answer The AD7730 has ESD protection diodes between the data lines and the DVDD and 
 GND rails on the chip. This means that in certain cases the digital section of 
 the device is powered via one of the digital inputs and via the ESD protection 
 diode.
 
 You should be aware that this may damage the device. The absolute maximum 
 ratings state that 
 "Digital Input Voltage to DGND . . . . -0.3 V to DVDD + 0.3 V"
 
 If DVDD is 0V then there shouldn't be any voltage on the digital inputs greater 
 than -0.3V to +0.3V. The 1k resistors that you have placed in series will 
 probably prevent any damage occuring to the IC, but it is undesirable to have 
 the digital section of the IC powered in this unreliable way (power supply is 
 high impedance and not always present). The AD7730 should therfore be powered 
 before being plugged into the printer port of the PC.

Question 2

AD7730: RDY signal not working

Accepted Answer

Question I try to program the AD7730 according to the example on page 36-37 of the data 
 sheet. The AD7730 is connected to a atmel at90s8535 microprocessor which 
 programs the registers. If I connect the RDY pin of the AD7730 to a 
 oscilloscope I dont see the signal going low (as in Wait for RDY low), it 
 always stays high. Is it neccesary to add a pull up or pul down resistor of to 
 use a buffer of something like that? Answer Pull up/down resistors are not required at the RDY line.
 
 A few notes:
 f you have established proper communication between the AD7730 and your micro, 
 you should be able to read back the contents of the registers that you have 
 programmed?? Is that possible.
 
 If you cannot, then you will need to verify your code by connecting a scope to 
 SCLK, DIN of the ADC to verify that the correct information is being sent to 
 the ADC.
 
 If you succeed in reading back the contents of the ADC registers, then you 
 should scope the RDY line after initiating a conversion…try changing to 
 continuous conversion mode, and you should see RDY changing at the o/p data 
 rate.
 
 1) The following conditions could prevent the /RDY line from updating. 
 * The /RESET is pulled low
 * The FSYNC is pulled set
 * The STBY bit is set or the STANDBY pin is low
 * The /RDY pin is pulled low externally
 
 2) In the error condition, try communicating with the part, for example write 
 to the communications register and try to read back from the Communications and 
 the setup register. Does the part respond correctly?.
 
 3) Look for the possibility that you inadvertently write to the Communications 
 register. We generally recommend that DIN is pulled high when the part is idle 
 to ensure that any activity on SLCK is ignored.
 
 4) Try resetting the digital interface by writing 32 1s to the part. Does this 
 recover correct operation?

Question 3

AD7730: Load cell

Accepted Answer

Question We are currently researching the subject of weighing using strain gauges and 
 the AD7730 ("almost all in one") seems to be quite suitable for that job.
 Our question is: Since a 10V excitation seems popular in the market for this 
 application, we would like to have an idea of how to work with a 10V excitation 
 and the AD7730 (or an AD similar chip). Answer If you are working with a standard 2mV/V load cell and a 10V excitation 
 current, this will give you a Full Scale input range of 20mV at the AD7730.
 
 If you were using a 5V excitation current with the same load cell, your full 
 scale would be 10mV, and therefore you would be effectively loosing one bit of 
 resolution.
 
 The problem is that the AD7730 is designed for a power supply of 5V (+4.75 to 
 +5.25) and will not tolerate a power supply of 10V (it will destroy). Therefore 
 if you want to use the 10V excitation, you cannot apply it directly at the 
 power supply pins of the converter. You will need a Voltage Regulator to 
 provide the +5V signal. Check the ADP3335ARM-5 for this purpose:

Question 4

AD7730: Increase in resolution

Accepted Answer

Question I am currently using your AD7730 parts to interface directly to a 2mV/V strain 
 gauge bridge with an excitation of 5V. We would like to use this type of part 
 for many reasons however, 
 it is proving that the resolution achievable is not high enough. I am idealy 
 looking for 20 bits at around 
 5Hz and maybe 18 at 100Hz. I am happy to consider another device and perhaps 
 some external analog amplification before conversion if you feel this is the 
 only option. Answer First thing to do is compare the expected resolution with measured resolution. 
 
 2mV/V bridge with a 5V supply gives a 10mV full-scale. With the PGA set for 
 gain of 128, CHOP enabled and the output update rate set to it’s minimum value 
 of 50Hz, the noise is 40nVrms. The effective resolution is 10mV/40nV = 250k 
 codes or 17.9bits. The peak to peak resolution is 10mV/(40nV x 6.6) = 37.8k 
 codes or 15.2bits.
 
 The AD7730 and AD7730L remain state of the art for weigh-scale and bridge 
 signal conditioning. 
 
 A couple of options for improving resolution are:
 
 · Quickest and easiest solution is to increase the excitation voltage. 
 
 · Use a digital post filter. The minimum output update rate of the AD7730 is 
 50Hz, using a digital filter (a simple moving average filter implemented in a 
 DSP or micro) to decimate to 5Hz and low pass filter can increase the 
 resolution by up to 2.5bits. Doubling the sample rate improves signal to noise 
 ration by 3dB or 0.5bits. 
 
 · You could look at building a low noise pre-amp. But you need to ensure that 
 the output referred noise of the preamp is approx 3x less that the noise 
 contribution of the AD7730 in the gain range to be used. For example, using 
 the AD7730 in gain of 16, noise is 115nVrms. You need to build a preamp with 
 output referred noise less than ~40nVrms. For a gain of 4, you need input 
 referred noise of 10nVrms or 66nVpeak to peak. The AD797 with typical low 
 frequency noise of 50nVpp could be used but you would need to compensate for 
 the offset, input bias current, temperature drift of this opamp. You also need 
 to remember that a 1k resistor at room temperature has noise of 4nV/root(Hz). 
 There’s a lot of work in designing a low noise preamp.

Question 5

AD7730: Required capacitance across the XTAL/ Resonator

Accepted Answer

Question I want to use a 4.91 Mhz ceramic resonator from Murata, which has integrated 
 capacitors, to earth of 15pF. How can I be sure, this will startup probably? 
 What is the recommendation for the Xtal and related capacitors. Answer The crystal or ceramic resonator is connected across the MCLK IN and MCLK OUT 
 pins, as per Figure 17.
 Capacitors C1 and C2 on the XTAL may or may not be required and may vary in 
 value depending on the crystal/resonator manufacturer's recommendations. So 
 therefore in this case as the capacitors are integrated this is not an issue.
 The AD7730 has a capacitance of 5 pF on MCLK IN and 13 Pf on MCLK OUT so, you 
 could check with Murata if this additional capacitance will effect to get the 
 crystal/resonator operating at its correct frequency.

Question 6

AD7730: Using the chop mode

Accepted Answer

Question We have used the AD7730L for some years now and are using the converter in
 chop mode, which gives us some problems with the frequences going through
 around the sampling frequence, so my question is: Our weighing cycle is 2-3
 seconds but we only need the A/D values for a short period of the 2 seconds,
 about 0,2 seconds. It is possible to avoid the drift if we run 1,8 s with
 chopping and 0,2 s without chopping. Will this be a better solution
 regarding drift than if you do not use chopping at all? Answer Using the AD7730 in chop mode effectively elliminates the internal offset from 
 the AD7730, by switching to non-chop mode, the result will be different from 
 chop mode as the offset that has increased with drift will now be included in 
 the result.
 
 When you calibrate the AD7730 periodically for zero scale offset you 
 effectively achieve the same result as using the part in chop mode - 
 therefore, as you have sufficient time to calibrate between conversions, I 
 would suggest to operate the device in non-chop mode and perform an internal 
 zero scale calibration between conversions to elliminate the offset introduced 
 by drift.

Question 7

AD7730: Parallel port of the PC

Accepted Answer

Question AD7730 is directly connected to LPT1 port of a PC.
 Din -> LPT1 :B0
 Clock -> LPT1 :B1
 Dout -> LPT1 :SEL INPUT
 
 All pins of AD7730 seem well connected.
 
 Problem is :
 1. We send 32 clocks with Din=1 to reset the part - Ok.
 2. We send 8 clocks with Din 00010000 (To read Status register).
 3. We send 8 clocks and we read Dout wich answers 10010111
 4. Dout stay at level 1 forever, even if we restart step 2.
 
 5. If we repeat this restarting at step 1, Dout answer once but after it stay 1 
 forever.
 6. Dout goes High (1) very slowly (9uS) while giving the 3 LSB of status 
 register on step 3.
 
 Clock on time = 3uS
 Clock off time = 6 uS.
 Delay between steps 1,2,3,4, is some seconds because started manually by 
 pressing key on keyboard. Answer The AD7730 should not be connected directly to the parallel port of the PC. The 
 digital signals from a parallel port are very noisy, prone to voltage spikes 
 and over-shoots. In addition, the edges are poorly defined and this can cause 
 problems interfacing to AD7730 (or any mixed signal IC). 
 
 Good practice is to place a schmitt trigger buffer between the P Port and the 
 AD7730. Refer to our evaluation board for further details. Or better still, 
 save your self some valuable time and buy the eval board. 
 http://products.analog.com/products/info.asp?product=AD7730
 
 you can order the eval board from any of our distributors. You can find you 
 nearest contact at the following webaddress:
 http://www.analog.com/world/corp_fin/sales_directory/distrib.html

Question 8

AD7730: Matching between different gain steps/stages

Accepted Answer

Question There was at least one important question left: How good is the matching 
 between the different gain steps/stages (1,2,4,.. etc.) of the PGA for example 
 in the 7730 or 7714.
 
 Concerning this topic you talked about some kind of application notes about how 
 to calibrate mV inputs using the PGA with higher gain when only having a 2,5 V 
 Reference for full scale calibration. Could you please send this information to 
 me ? Answer The answer to your question is "it depends". It's different for the AD7730 and 
 AD7714 and depends on whether you use the AD7730 in Chop mode or not. I have 
 included a presentation which takes the form of Frequently Asked Questions. 
 It's not really an app note but there's a lot of useful information in there. 
 If this doesn't answer your specific question, let me know. 
 
 In addition, many designers want to use the AD7730 with input ranges other than 
 those given in the datasheet, for example if there's a requirement for a 60mV 
 full-scale. The notes below explain how you can adjust the calibration 
 registers directly for different full-scale ranges and to subtract known 
 (static) bridge offsets. 
 
 " There are a couple of ways that the designer can approach this problem. The 
 first and simplest is to do a system offset cal and a system fullscale ca on 
 the device for his offset and fullscale conditions. 
 The second method is to adjust the calibration coefficients in the part for the 
 desired operation The following details how this can be achieve, examples are 
 attached.
 
 To adjust the offset register the following needs to be done.
 
 1. Perform a self gain calibration (This will corrupt the Offset Register)
 The purpose of this is to adjust for the actual gain of the part, which is 
 nominally 31.25 on the 80mV range.
 
 2. Perform a self offset calibration. For CHP=1 this will be close to 800000

For the 80mV range, 1 Offset Register LSB corresponds to 13.2975nV, assuming a 
 gain of exactly 31.25, and the correct reference is used (2.5V with Hiref=0 or 
 5V with Hiref=1). This nominal LSB needs to be scaled to correct for the part's 
 actual gain and the actual reference used.
 
 1LSB = 13.2975E-9 * VREF * Actual Gain Register
 --------------------------------------------
 VREFnom * Default Gain Register VREFnom=2.5Vor5V
 
 This should then be scaled depending on the range, e.g. divide by 8 for 10mV 
 Range.
 
 The code to be added/subtracted to/from the offset register is then determined 
 by dividing the external offset to be removed by the LSB calculated.
 
 Therefore, assuming a gain of 31.25, and a default reference, then if an 
 external offset of 10mV is to be subtracted, 752021(decimal) should be added to 
 the offset register result obtained to produce 8B7995(Hex). If an external 
 offset of 10mV is to be added, 74866B(Hex) should be written
 to the offset register. 
 
 If the DAC is being used, the above calculations would change, however given 
 that the DAC does not subtract a precisely defined offset, it is not likely to 
 be used in conjunction with the above method.
 
 The gain register is simpler to manipulate for system full-scale. The procedure 
 here is to:
 1. Perform an internal gain cal
 2. Perform an internal offset cal (To correct corrupted offset register)
 
 The gain coefficient produced in 1 is then simply scaled by multiplying it by 
 the default Full Scale for the selected range, divided by the system full scale 
 analog input, then corrected for the actual reference:
 Adjusted Gain Reg = Initial Gain Reg * VREF * Nominal Full Scale Input
 -----------------------------------------------------
 VREFnom * System Full Scale Input 
 
 E.g. If the maximum analog input is 60mV, then for a 60mV input to produce 
 FFFFFF on the 80mV range, the gain coefficient should be multiplied by 80/60. 
 
 This system full scale input is the input after any offset has been removed by 
 the DAC or offset register.
 
 If adjusting of both the offset and gain registers is required in the manner 
 described above, then the offset register should be adjusted first, and the 
 gain coefficient obtained in step 1 scaled as above.
 
 -------------------------------------------------------------------------
 
 Here's a few more complicated examples of adjusting the Offset Register. They 
 all assume the 80mV range is selected, and an external 10mV offset is to be 
 removed.
 
 I. Vref = 5, Hiref = 1, CHP = 1, Gain = 31.25 (Same example as previously)
 1. Gain Cal -> 593CEA
 2. Offset Cal -> 800000
 
 13.2975E-9 * 5.0 * 593CEA
 1LSB = ------------------------- = 13.2975nV
 5.0 * 593CEA
 
 Code = 10mV / 13.2975nV = 752021 Dec [b7993 Hex]
 => Offset Register = 87b993

II. Vref = 4.5, Hiref = 1, CHP = 1, Gain = 31.25
 1. Gain Cal -> 593CEA
 2. Offset Cal -> 800000
 
 13.2975E-9 * 4.5 * 593CEA
 1LSB = ------------------------- = 11.98775nV
 5.0 * 593CEA
 Code = 10mV / 11.98775nV = 835578 Dec [cbffa Hex]
 => Offset Register = 8cbffa

III. Vref = 4.5, Hiref = 1, CHP = 1, Gain = 34.375 (X 1.1)
 1. Gain Cal -> 5120A1
 2. Offset Cal -> 800000
 
 13.2975E-9 * 4.5 * 5120A1
 1LSB = ------------------------- = 10.88nV
 5.0 * 593CEA
 Code = 10mV / 10.88nV = 919114 Dec [e064a Hex]
 => Offset Register = 8e064a
 (The actual gain will never be that far from the ideal)

IV. Vref = 4.5, Hiref=1, CHP=0(Inherent Offset of ~2mV), Gain = 34.375 (X1.1)
 1. Gain Cal -> 5120A1
 2. Offset Cal -> 7D31E3
 
 13.2975E-9 * 4.5 * 5120A1
 1LSB = ------------------------- = 10.88nV
 5.0 * 593CEA
 Code = 10mV / 10.88nV = 919114 Dec [e064a Hex]
 => Offset Register = 7D31E3 + E064A = 8b382d
 "

Question 9

AD7730: ESD protection

Accepted Answer

Question We are currently using AD7730 in our weighing indicators.
 The load cell input is connected to the AD7730 inputs with an EMI filter 
 (muRata DSS710), a 330 Ohm serie resistor and a 470 pF cap to GND.
 Now we are in the process of re-engineering some units andI would like to 
 improve the ESD/EFT immunity of the load cell input.
 Can you suggest a good solution to protect the AD7730 input against EMI and 
 ESD/EFT while maintaining the nominal performances? Answer Most ICs are protected against ESD hits of between 1kV and 3kV based on the 
 human body model. 
 From the point of view of the end manufacturer or OEM, equipment must pass the 
 CE-mark which means meeting IEC1000-4-2 for ESD protection, and IEC1000-4-4 
 for Electrical Fast Transient (EFT) Immunity. 
 These standards apply only to inputs and outputs which are directly accessible 
 by the end user. The IEC ESD protection standard normally requires equipment to 
 pass level 3 (8kV air discharge, 6kV contact discharge). It is the 
 responsibility of the end manufacturer to ensure that their equipment passes 
 these tests.
 We don't have any standard recommendation on how to protect circuits from ESD 
 damage as most manufacturers develop their own standard methods. Basically you 
 have to ensure that the energy from an electrostatic discharge is dissipated 
 long before it ever reaches the sensitive electronics. There are a number of 
 ways of doing this. Some methods include, a diode clamping circuit, tranzorbs, 
 sparkgaps on the PCB, capacitors to earth ground, a current limiting resistor, 
 and combinations of the above. 
 
 The final chapter in all our seminar books is dedicated to hardware design 
 techniques and deals with such issues as grounding, decoupling, parasitic 
 thermocouples and good PCB design. 
 
 Refer to chapter 9 of data conversion handbook: 
 http://www.analog.com/library/analogDialogue/archives/39-06/data_conversion_hand
 book.html

Question 10

Problems initiating calibration on AD7730

Accepted Answer

Question I have a project about measurement weight and inertia. I have used ad7730 3 
 items in the project. I couldnt calibrate them. I read PDF file many times. I 
 check it. Can you send me short pseudo code for calibrate it. Answer First check that you really have established communication with the AD7730 by 
 attempting to read the power on default values from the status register (CX 
 Hex) and the gain register (59AEE7 Hex). If you don't read back the default 
 values you need to review your digital interface and try to correctly establish 
 communication with the AD7730. Then you can start looking at how to calibrate. 
 
 Pseudo code for calibration is included in table XIX on page 37 of the 
 datasheet.

Question 11

Single Micrel FET MIC4427 driver

Accepted Answer

Question When using AC excitation, is it possible to use only one Micrel FET MIC4427 
 driver? Answer Yes you only need a single MIC4427.
 The AD7730 has 2 channels and you need to use both the OUTA and OUTB channels 
 simultaneously.
 The upper and lower sections of the bridge are driven via AC and are anti-phase 
 with each other
 (180 degrees different). That is why each end requires an inverter on 1 of the 
 transistors or FETs so that it is biased to turn on at the correct time.
 Two of the FETs are p-channel and the other pair are n-channel.

Question 12

Only achieving 10-bits of stable resolution, should be 13-bits or more

Accepted Answer

Question The target accuracy should be better than 13-bits, but I only can read 9 to 10 
 stable bits.
 The ADC is powered from a DC/DC converter followed by a filter.
 Avdd and Dvdd are powered from a different DC/DC converter. Answer With an update rate of 200Hz, 10mV bipolar input range, chop mode, you can 
 expect 80nVrms of noise or about 15-bits of noise free resolution. If you are 
 only seeing about 9 or 10-bits of noise free resolution, I would guess that the 
 DC/DC converter is probably feeding through to the converter and adding noise 
 to the conversion result.
 As a first test, ground the analog input pins (remove any input conditioning 
 circuitry) and disable the DC/DC converter. Use a clean bench top power supply, 
 or a battery plus linear regulator to power the AD7730. You need to ensure that 
 the DC/DC is removed from the system as noise could be coupling into the ADC as 
 ripple on the power supply or as radiated emissions. By doing this, it should 
 be possible to achieve the datasheet spec for resolution.

Question 13

Noise when switching from chop to non-chop mode

Accepted Answer

Question Noise is increased as I swtich from chop to non-chop mode. Why? Answer There will be a reduction in modulator noise of about 20-30% when the AD7730 is 
 used in non-chop mode compared to chop mode. However, when the AD7730 is used 
 in non-chop mode there will be a reduction in drift performance. Most weigh 
 scale applications will use the AD7730 in chop mode for increased drift 
 performance. 
 For the best line frequency rejection, you should set the output update rate to 
 be equal to the line frequency. The position of the first notch in the digital 
 filter is equal to the output update frequency.

Question 14

AD7730 Replacement - AD7195

Accepted Answer

Question What part would you recommend in place of the AD7730? Answer There is no direct replacement, but the AD7195 could be used in place of the 
 AD7730. It supports ac and dc excitation. The AD7195 is lower noise and lower 
 current than the AD7730.

Question 15

ADC for low range pressure transducer

Accepted Answer

Question We are developing medical device in the field of lung function measuring 
 devices. For our devices we currently use the AD7730 A/D converter with a 5 
 inch H2O preasure transducer. As we plan for a new device next year, we are 
 looking if the AD7730 is still up to date and suitable for our application, or 
 if there is a newer better A/D converter that could be used for our 
 application. Can you tell us about new products analog devices offers in that 
 range of AD converters, that might fit our design. Answer The AD7195 might be considered in place of the AD7730. It has lower noise and 
 lower power than the AD7730.
 
 http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad7195/produ
 cts/product.html

Question 16

AD7730 application question re 6-wire loadcell

Accepted Answer

Question I have a question related to the AD7730 Bridge Transducer ADC. In our 
 application we need to use both channels to connect two bridges of the same 
 type, and both of the bridges are in a six-lead configuration. I have a 
 question how to connect the reference inputs REF IN(+) and REF IN (-) terminals 
 in such case to obtain best results and take advantage of the IC performance. Answer When using a 6-wire loadcell, the 2 SENSE wires from the loadcell need to be 
 used as the reference to the ADC. So, when loadcell 1 is selected, its SENSE 
 pins need to be used as the reference to the AD7730. Similarly, when loadcell 2 
 is selected, the SENSE wires of loadcell 2 need to be connected to the REF pins 
 of the AD7730. To do this, an external mux or switch is needed so that you can 
 switch between the SENSE pins of loadcell 1 and loadcell 2.
 
 The AD7190 could be used in place of the AD7730 if you are using DC excitation. 
 The AD7190 has 2 reference inputs – REFIN1 and REFIN2. Therefore, the SENSE 
 pins of each loadcell could be connected permanently to the AD7190. You would 
 then only need to select the appropriate reference source (REFIN1 or REFIN2).

Question 17

AD7730: Can't get 24-bit resolution

Accepted Answer

Q 
 I can't 24bit resolution from this part at an output data rate of 50Hz. Why? 
 
 A 
 At an output update rate of 50Hz, you don't have 24bits of resolution available. You can use the noise tables on pages 10 and 11 of the datasheet to predict the resolution for a given Input range and update rate. You can see that for a 50Hz output update rate ( this also locates the first filter notch at 50Hz and all subsequent filter notches at multiples of 50Hz) and an input range of 20mV the maximum resolution is 17bits. You will get 24 bits out of the part, i.e. the digital word length is 24bits, but the peak to peak resolution of the measurement is 17bits or 120,000 counts. At this level you are limited by the quantisation noise inherent in the conversion process.

Question 18

AD7730: When /CS is high, is DOUT is in tri-state mode

Accepted Answer

Q 
 I have an application with a system that has three AD7730s; they have a serial communication with a /CS signal. When /CS is high, is DOUT is in tri-state mode? 
 
 A 
 The DOUT line goes into a high impedance state some time (between 10ns and 80ns) after the last inactive edge on SCLK (e.g. if POL = 1 data is clocked out on the falling edge and therefore the rising edge is inactive). See datasheet for precise timing. The leakage current when DOUT is in tri-state is 10uA max (page 3, Logic Outputs section). So in answer to your question, it is possible to connect the DOUT pins for all three devices on condition that only one at a time is outputting serial data to the bus. For this reason, the user should leave sufficient time between releasing the /CS line on one AD7730 and asserting the /CS line for a second device, in order that the first device has time to relinquish the bus before the second device starts driving the bus.

Question 19

AD7730 Internal-zero-scale calibration

Accepted Answer

Hi, I am using the AD7730 and i have some problems with the Internal zero-scale calibration. I use the SPI interface to communicate between my uC and the AD converter. 
 I am able to wirte and read from the registers of the AD7730. 
 The converter is configured in bipolare mode, HIREF = 1( 5V ), Range : +-10mV, 16bit mode. 
 I am using two AD7730 parallel which are selected with two CHIP-Select. 
 
 After a calibration cycle the value of the corresponding Offset-Register changed by a very small value but there is still an offset(approx. 30150) to the expected value of 32768 when the input pins are shorted. 
 
 Has anyone any advices?

This FAQ was generated from the following discussion: AD7730 Internal-zero-scale calibration

Question 20

AD7730

Accepted Answer

Q 
 I have to realize an A/D board with four ADCs (AD7730). The input signals are in 0-10 mV range, and I need at least 14 bits of resolution or greater. I have built an evaluation board to test converters' performance, but I am not satisfied. I have noted that the sclk signal is very critical and the adc introduce a lot of noise (I have only 10 bits of resolution). Nevertheless I think that the problem is my demo-board and not adc part. 1) Could you send me any information about AD7730, layout and routing circuit problems ? 2) How can I reduce adc's noise effects ? 3) How can I deliver sclk signal to four adcs ? 4) Is it usefull amplifing and filtering input signal to reach max adc input range ? 
 
 A 
 To properly specify the expected resolution of the AD7730, you must need to quote, the input range you are using, output update rate and the status of the CH=P BUF and BIPLOAR bits. You can then refer to the noise tables on pages 10 and 11 of the datasheet to determine the expected noise performance and resolution. For example for a 0-10mV input range with a 50Hz update rate, you can expect a peak to peak resolution in excess of 15bits. However, if you set the update rate to 1200Hz, the peak to peak resolution will only be 13.5bits. I would tend to agree with your assessment that the most likely cause is the layout of your PCB. The device noise of the AD7730 is of the order of 160nV rms provided the bandwidth is kept low by keeping the output update rate low. As you increase the bandwidth, more device noise will be present in the output and eventually as you increase the bandwidth further, the quantisation noise of the conversion process will start to dominate and the resolution will fall off drastically. 1) We have an evaluation board available for the AD7730, details are given on our website. The eval board shows the recommended layout for a single AD7730. A few notes on grounding for sigma delta converters follow: The pin marked DGND on the AD7731 is the return path for the digital current out of the AD7731. It does not necessarily mean that this pin should be connected to the digital ground plane of your system. Connect the AGND pin and the DGND pins of each individual IC together with a broad, low inductance track. You can now treat each of these seven nodes as a single analog ground connection to be routed onto your system analog ground plane. You should provide a separate ground return path back to the power supply for each converter in the system. If each AD7730 has 7mA of analog current and 1mA digital, providing separate return paths means that there is only ever 1mA digital current in each converters local ground plane. You can do this by flooding the analog ground plane and sectioning it off with cuts to provide a local ground return path for each converter. The digital current from the AD7731 is relatively small in comparison to the analog current and provided you use low inductance ground paths this small amount of digital current should not adversely affect the noise floor. You should ensure that AVDD is decoupled to AGND and DVDD is decoupled to DGND. The system analog ground plane should be kept separate from the system digital ground plane, which routes the return current for the &ldquo;spikey&rdquo;, digital components such as micro-controller, digital buffers, logic etc. The connection between the system digital ground and system analog ground should be made at a single point (commonly referred to as the &ldquo;star point&rdquo;). Where you place the star point will depend on your system but this is often determined by the power supply you use. The single connection between analog and digital ground is already made at the power supply. Your job as a designer is to ensure that no digital current is allowed to flow in the analog ground plane while ensuring that the potential of the analog and digital grounds in your system remain equal. The final chapter in all our seminar books is dedicated to hardware design techniques and deals with such issues as grounding, decoupling, parasitic thermocouples and good PCB design. http://www.analog.com/support/standard_linear/seminar_material/index.html 2) The ADC is not inherently noisy. As described above the noise in the ADC is a trade off between update rate and resolution required. If you have noise in your system which is limiting the peak to peak resolution to 10bits, this could be due noise or spurious signals on the inputs, a noisy power supply ( if you have a switched DC DC converter in your power supply, this can generate a lot of noise), or it could be due to poor grounding in the system which allows high frequency digital currents to move the ground potential around. 3) The SCLK is not related to the master clock frequency in any way. You should have a separate crystal supplying the master clock to each ADC. Your system should then read each ADC in response to DRDY going low. You can only address one ADC at a time therefore the delivery of SCLK to all four ADCs should not be critical. Where you might have an issue is if SCLK is not shielded and can couple into the input or the power supply (or both). When tracking SCLK around your system, ensure that you have ground below at all times and ground on both sides of the SCLK track. Look for places in your PCB where SCLK could couple onto other lines. 4) Amplifying an input signal which starts in the 10mV range will almost certainly add more noise into the signal of interest. Most opamps will be dominated by 1/f noise, and generally in sensors it's the low frequency information you are interested in. Designing a pre-amp will be a very difficult design job. I would suggest that interfacing directly to the AD7730 with a single RC anti-alias filter will yield the best results in the shortest time. Once you can get the AD7730 operating correctly you should be able to achieve up to 16 bit peak to peak resolution.

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AD7730: FAQ