AD7266: Timing for analog input selection to CS falling

Question What is the min time from Analog input selection ( A0-A2) to CS falling Edge. I can't find this information in the datasheet ! And I have some problems when I do analog input scanning 1- 6. SCLK speed 24.5MHZ AVDD = VDD = 5V external VREF = 4.096V SGL = 1 fixed VDRIVE = 3.3V Answer For the AD7266 you need to have the logic levels on the channel selection pins setup prior to the acquisition time for the part. The Tacq on figure 31 page 17 of the AD7266 datasheet actually refers to the Acquisition time for the part. This time is details on page 4 of the datasheet as "Track and hold Acquisition time". This is 90ns for Vdd =5V and 110ns for Vdd = 3V. In your application you need to have the channel selected prior to the acquisition time to ensure the correct conversion result. So in your case using a 5V Vdd if you have the channel selection pins setup 95ns before you brought CS low to initiate a conversion you would be well inside the specification.You much not change the logic level on the channel selection pins during the conversion. You can changes the state of these pins once the ADC returns to track mode which is on the 13th rising SCLK edge after CS falling edge. The CS falling edge initiates the conversion. The conversion result bits are clocked out on the falling edge of the SCLK input and 14 SCLKs are required to access the data. The data stream consists of two leading zeros followed by the 12 bits of conversion data. The data is provided MSB first. The output result for the AD7265 is for the selected channel. So after the 13th SCLK rising edge you can select the next channel for conversion and once CS is brought low the selected channel is what is converted and the result that is simultaneously read is for that channel. The conversion and read occur together effectively. So if you select a channel, say channel1, allow adequate acquisition time, apply CS falling edge, read conversion result will be for channel 1.

Is the AD7266 sensitive to SEU (Single Event Upset)?

Question Is the AD7266 sensitive to SEU (Single Event Upset)? Answer We do not test for SEU type events during the AD7266's qualification phase. Therefore, I don’t believe we can provide you with a firm statement on the AD7266 sensitivity to SEU. The reliability engineer's opinion is that particle induced damage should not be a concern for process node used for this product. We cannot tell you more than this.

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AD7266 Production
The AD7266 is a dual, 12-bit, high speed, low power, successive approximation ADC that operates from a single 2.7 V to 5.25 V power supply and features...
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+Documents
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-AD7266: FAQ
- AD7266: Timing for analog input selection to CS falling
- Is the AD7266 sensitive to SEU (Single Event Upset)?
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