Question 1

What layout strategies and design techniques help ensure optimal performance when working with the AD7768 ADC?

Accepted Answer

It is recommended to use our AD7768 Evaluation Board | Analog Devices design example as a reference for a good layout. 
 There is also DN477 - Driving Lessons for a Low Noise, Low Distortion, 16-Bit, 1Msps SAR ADC and Design Guidelines for High-Performance, Multichannel, Simultaneous-Sampling ADCs in Data-Acquisition Systems (DAS) | Analog Devices describing design techniques to achieve the desired ADC performance.

Question 2

AD7768: What is the analog input range?

Accepted Answer

The input voltage range of the ADC depends on the analog voltage supplies (AVDDx and AVSSx), the reference used (Vref), the configured PGA gain and the type of signal connected to the input (single ended, differential, and pseudo-differential).

Input signal type 
 Input signal type 
 AVDD from GND 
 AVSS FROM GND 
 Vref from GND 
 VCM from GND 
 AINx+ max without limitation 
 AIN+ min without limitation 
 AINx- max without limitation 
 AIN- min without limitation 
 Absolute maximum Voltage Rail 
 Absolute Minimum voltage Rail 
 AIN+ max 
 AIN+ min 
 AIN- max 
 AIN- min 
 max{(AINx+)-(AINx-)} 
 min{(AINx+)-(AINx-)}

Bipolar Supply 
 True differential 
 2.5 
 -2.5 
 4.096 
 0 
 2.048 
 -2.048 
 2.048 
 -2.048 
 2.5 
 -2.5 
 2.048 
 -2.048 
 2.048 
 -2.048 
 4.096 
 -4.096

Pseudo Differential 
 2.5 
 -2.5 
 4.096 
 0 
 4.096 
 -4.096 
 0 
 0 
 2.5 
 -2.5 
 2.5 
 -2.5 
 0 
 0 
 2.5 
 -2.5

Single ended 
 2.5 
 -2.5 
 4.096 
 - 
 1.696 
 -2.4 
 -2.4 
 -2.4 
 2.5 
 -2.5 
 1.696 
 -2.4 
 -2.4 
 -2.4 
 4.096 
 0

Unipolar Supply 
 True differential 
 5 
 0 
 4.096 
 2.048 
 4.096 
 0 
 4.096 
 0 
 5 
 0 
 4.096 
 0 
 4.096 
 0 
 4.096 
 -4.096

Pseudo Differential 
 5 
 0 
 4.096 
 2.048 
 6.144 
 -2.048 
 2.048 
 2.048 
 5 
 0 
 5 
 0 
 2.048 
 2.048 
 2.952 
 -2.048

Single ended 
 5 
 0 
 4.096 
 - 
 4.196 
 0.1 
 0.1 
 0.1 
 5 
 0 
 4.196 
 0.1 
 0.1 
 0.1 
 4.096 
 0

XLSX

Question 3

EVAL-AD7768 Evaluation Board Quick Start Guide

Accepted Answer

The EVAL-AD7768FMCZ evaluation kit features the AD7768, a 24-bit, 256 kSPS, analog-to-digital converter (ADC). This aim of this document is to create a quick start guide for the AD7768/AD7768-4 customer evaluation board and to provide a support forum for any FAQs relating to initial set up of the evaluation boards. This post can be used for both the AD7768 and AD7768-4 evaluation boards ( 8 channel and 4 channel devices respectively) as both boards are configured in the same way. 
 The EVAL-AD7768FMCZ can be used as a standalone board for development or in conjunction with the EVAL-SDP-CH1Z high speed controller board. This document assumes the EVAL-AD7768FMCZ is being used in conjunction with the EVAL-SDP-CH1Z. 
 Quick Start 
 
 Ensure that the EVAL-SDP-CH1Z board is disconnected from the USB port of the PC. Install the evaluation board software from the CD included in the evaluation board kit, or alternatively from the evaluation board web page. Restart the PC after the software installation is complete. (For complete software installation instructions, see the Software Installation Procedures section in the User Guide.) 
 Connect the EVAL-SDP-CH1Z board to the EVAL-AD7768FMCZ board (unpowered). The attached image illustrates this connection: J4 of the EVAL-SDP-CH1Z board adapts to the receiving socket (P1) on the EVAL-AD7768FMCZ printed circuit board (PCB). 
 Apply power to the EVAL-AD7768FMCZ board via the supplied 9 V dc adapter at J1. LK1 must be in Position B. 
 Connect the 12 V dc supply to the EVAL-SDP-CH1Z board, and then connect to the PC using the supplied USB cable. 
 Launch the AD7768 evaluation software from the Analog Devices subfolder in the Programs menu. 
 Configuration of the AD7768 can be carried out using the software, in both the configuration tab and the register tab. Pressing the sample button on the top right of the AD7768 software window will sample the input of the ADC and the software displays the respective waveform, FFT and histogram of the sampled data. 
 
 Alternative Power Options 
 If preferred, there are a number of options to supply power to the board. 
 
 Connector J3 can be used to supply between 7V and 9V to the board, between V+ and GND. This is done by setting LK1 to Position A. (V- does not need to be connected). This power is then supplied to the on board regulators (ADP7118 from Analog Devices) which supply 5V to AVDD1 and AVDD2 and 3.3V to IOVDD. 
 Connector J2 can be used in the case where supplies other than the default evaluation board supplies are to be used. Please see the Power Supplies section of the datasheet for the full range of operating voltages. This can be selected by changing solder links SLP1, SLP2 and SLP4 to power AVDD1, AVDD2 and IOVDD respectively. Please note that the on board reference, amplifiers and VCM buffer will still need to be powered up in this case from either J1 or J3. 
 
 Analog Inputs 
 The analog input signal can be applied using either the SMB connectors for an ac signal, or using the terminal blocks for a dc signal. By default the signal is buffered on each channel using the ADA4896-2. For evaluation, this can be bypassed by changing the solder links labelled SLX+ and SLX-, where X is the channel number of interest. 
 The VCM voltage is applied at the input of each of the driver amps from the output VCM (pin 59) of the AD7768/AD7768-4 by default. This is buffered using the OP2177 and supplied to each analog input. The option to bypass this buffer is provided for by solder link SL15. A resistor divider can also be utilised in order to get any fraction of AVDD1 for the VCM voltage by changing SL19 to position B and by adjusting R166 and R167 accordingly. Please see the schematic and user guide on the evaluation board web page for more details. 
 Input Amplifiers 
 The input signal is driven with the ADA4896 and passed through a low pass anti-aliasing filter. The on-board ADA4896-2 input driver amps are powered using U1 on the board, the ADP7118. This supply can be changed using the solder link options SL_AMP+ and SL_AMP-. The amplifiers will then take their supply voltage from either J1 if LK1 is set to position B, or J3 if LK1 is set to position A. If a negative supply is needed it can be applied using J3 at the V- terminal. 
 Please note in order for a negative voltage to be applied at J3 the resistors present on pin 4 of all eight of the ADA4896-2's will need to be replaced with decoupling capacitors. These resistors are shorted to ground in the default configuration. 
 Remember: Full specifications on the AD7768 and AD7768-4 are available in the product data sheet, which should be consulted in conjunction with user guide, UG-917 when working with the evaluation board. 
 1. Ensure that the EVAL-SDP-CH1Z board is disconnected from the USB port of the PC. Install the evaluation board software from the CD included in the evaluation board kit. Restart the PC after the software installation is complete. (For complete software installation instructions, see the Software Installation Procedures section.) 
 2. Connect the EVAL-SDP-CH1Z board to the EVAL-AD7768FMCZ board (unpowered). Figure 1 illustrates the connection: J4 of the EVAL-SDP-CH1Z board adapts to the receiving socket on the EVAL-AD7768FMCZ printed circuit board (PCB). 
 3. Ensure that the boards are connected firmly together. 
 4. Apply power to the EVAL-AD7768FMCZ board via the supplied 9 V dc adapter at J1 (LK1 in Position B). Alternatively, supply an external voltage in the range of 7 V to 9 V from a bench top power supply using the J3 connector (LK1 in Position A). 
 5. Connect the 12 V dc supply to the EVAL-SDP-CH1Z board, and then connect to the PC using the supplied USB cable. For Windows XP, the PC may need to search for the EVAL-SDP-CH1Z drivers. Choose to automatically search for the drivers for the EVAL-SDP-CH1Z board if prompted by the operating system. 
 6. Launch the AD7768 evaluation software from the Analog Devices subfolder in the Programs menu. 
 
 Attachments:

Question 4

EVAL-AD7768FMCZ FAQ - How can I save sample data to a file?

Accepted Answer

Data displayed on any of the graphs in the EVAL-AD7768FMCZ/ EVAL-AD7768-4FMCZ can be saved to a file for further processing. There is the option to export the data to the clipboard or to excel. This can be done by right clicking the graphs and selecting the export option. 
 Sample data for analysis and a head start on evaluation of the EVAL-AD7768FMCZ/EVAL-AD7768-4FMCZ can be found here

Question 5

Interfacing the AD7768/AD7768-4 to a microcontroller

Accepted Answer

The AD7768/AD7768-4 outputs data as a master, meaning that the device continuously streams data and it is the user's task to read the data as it is output. Therefore the microcontroller that interfaces to the data output lines must be configured as a slave. (A separate interface needs to be configured if SPI control is required. If not, the AD7768/AD7768-4 can operate in pin control mode) 
 The AD7768/AD7768-4 data interface has been tested by reading data using the Serial Audio Interface (SAI) on a microcontroller. For this example all 8 channels of AD7768 were output on DOUT0. 
 Connections Required 
 The connections required for the data interface on the AD7768 side are: 
 
 DRDY - this is the flag that signals new data is ready to be read. 
 DCLK - this is the data output clock. 
 DOUTx - this is the pin the data is output on. The AD7768 can output data on 1, 2 or 8 DOUT pins. The AD7768-4 can output data on 1 or 4 DOUT pins. DOUT0 was used for this test case. 
 
 The connections required to the microcontroller are: 
 
 FS (frame start). Used to signify a new conversion result is being output by the AD7768/AD7768-4 . Connect this pin to DRDY on the AD7768/AD7768-4 
 SCLK (the interface clock) Used to clock the data into the microcontroller. Connect this pin to DCLK on the AD7768/AD7768-4. The master supplies the clock for the transaction, DCLK in this case. DCLK on the AD7768/AD7768-4 can be configured as a divided down version of the master clock (MCLK). 
 SD. (Serial data input) In the case where one DOUT is being used, this pin needs to be connected to DOUT0 on the AD7768/AD7768-4. 
 
 Configuring the Interface 
 The microcontroller interface needs to be configured to accept the data output from the DOUT pins. For this example, all 8 channels of data are output on DOUT0 for the AD7768. Data is being read on the SAI interface which is configured as follows: 
 
 Configure the SAI as an asynchronous slave 
 Set the frame length to 256 bits. Data size is 32 bits. (32 bits x 8 channels = 256 bits total every DRDY) 
 Save data to 8 slots, each of 32 bit size 
 
 Configuring the AD7768 
 
 On the AD7768 configure FORMAT0 and FORMA1 pins to logic 1. This outputs all data on DOUT0. 
 Set the DCLK frequency to MCLK/1 
 The output data rate (ODR) can be set from the slowest possible rate up to 128kHz. If the max ODR of 256kHz is needed, two DOUT pins must be used to read all the data. 
 
 Note: On the AD7768-4 since there are only 4 channels the same constraint does not apply.

Question 6

AD7768 SYNC vs. RESET

Accepted Answer

The AD7768 is an 8-channel, simultaneous sampling &Sigma;-&Delta; analog-to-digital converter (ADC) with a &Sigma;-&Delta; modulator and digital filter per channel, enabling synchronized sampling of ac and dc signals. The AD7768 achieves 108 dB dynamic range at a maximum input bandwidth of 110.8 kHz, combined with typical performance of &plusmn;2 ppm integral nonlinearity (INL), &plusmn;50 &mu;V offset error, and &plusmn;30 ppm gain error. 
 Two important commands on the AD7768 are the SYNC and RESET commands. This FAQ aims to clarify the difference between the two functions, what they do, and when they are required. 
 SYNC 
 The SYNC command can be thought of as a reset of the digital filter paths and logic within the AD7768. One of the major events that the sync triggers is the reloading of the digital filter coefficients based on the selected configuration. A SYNC should be provided to the AD7768 after any changes to the AD7768 configuration, before valid samples are acquired. It should also be provided after a RESET or after initial power-up when in pin control mode or when no SPI configuration changes are required. 
 If a SYNC is not provided after a configuration change, then, for example, the digital filter coefficients used may not be correct for that configuration. In this case, an unexpected filter profile could be used, until a SYNC is provided. 
 The sync signal can be provided direct to the AD7768 SYNC_IN pin, to the START pin, or can be triggered over SPI, under software control. To provide the SYNC over SPI or through the START pin, the SYNC_OUT and SYNC_IN pins must be tied together. 
 Once the SYNC is provided, it is no longer required to provide a SYNC again, until either the part is reset, or the configuration is changed. 
 RESET 
 The RESET command causes a full reset of the AD7768, and the device is set to it's default configuration. It is useful to put the AD7768 into a known valid configuration, with all internal registers set to default values. 
 The default configuration is as follows: 
 - Eco power mode with MCLK/32. 
 - Interface configuration of DCLK = MCLK/8, header output enabled, and CRC disabled. 
 - Filter configuration of Channel Mode A and Channel Mode B is set to sinc5 and decimation = &times;1024. 
 - All channels are assigned to Channel Mode A. 
 - Analog input precharge buffers are enabled on all channels. 
 - Reference precharge buffers are disabled. 
 - The offset, gain, and phase calibration registers are reset to the factory settings. 
 - Continuous conversion mode is enabled. 
 For more information search for AD7768 at: Search | Analog Devices

Question 7

AD7768 FAQ - What front end driver amplifier is suitable to drive the AD7768?

Accepted Answer

There are many amplifiers suitable to drive the AD7768/AD7768-4. Choosing the most suitable amp can be a difficult task, especially when there are constraints on the system power. In order to achieve the lowest power and highest accuracy in a data acquisition (DAQ) system the following application note can be used as a starting point to select the most suitable driver amplifier: 
 Modular Data Acquisition (DAQ) Footprint Using the AD7768/AD7768-4 
 
 This application note outlines how to achieve &minus;126.6 dB of total harmonic distortion (THD) at subsystem power levels as low as 19.5 mW per channel. 
 The driver amplifier and RC filter combinations recommended in this document apply to the AD7768, AD7768-4, and also to the AD7768-1 New which is single-channel version of the same AD7768 family. Updated

Question 8

If I enable the analog input buffers on the AD7768 (or AD7768-4, AD7768-1New, AD7761) do I still need an external ADC driver opamp?

Accepted Answer

If I enable the analog input buffers on the AD7768 (or AD7768-4, AD7768-1 New , AD7761) do I still need an external ADC driver opamp? 
 
 The precharge buffers are not full buffers and do not replace the external driver opamp(s). Some further details on how to choose a suitable driver amplifier in combination with the enabled or disabled precharge buffers is available in this application note on design of a modular DAQ subsystem: Modular Data Acquisition (DAQ) Footprint Using the AD7768/AD7768-4

The precharge buffers are not full buffers and do not replace the external driver opamp(s). The analog input precharge buffers provide the initial charging of the internal switched capacitor network during the first ~25% of the sampling phase. For the remaining ~75% of the sampling phase, the buffers are automatically bypassed, and the fine accuracy settling charge is provided by the external driver. This eases the driving requirement of the external opamp(s), and in some cases allows lower power opamps to be used. 
 
 The amount of time that the precharge buffer is active is ~15ns in full power mode, ~29ns in median power mode, and ~116ns in low power mode. So this equates to approximately 25% of the sampling period, when the modulator is used at the maximum rate, for each power mode. If the modulator is run at a lower rate then the precharge buffer is still enabled for the same length of time, which becomes a smaller portion of the overall sampling period. 
 
 When enabled, the AD7768 internal sampling capacitors are charged close to the input voltage by these on-chip analog input precharge buffers, before the external driver is connected to the sampling capacitors. This eases the driving requirement of the external network. The analog input precharge buffers reduce the switching kickback from the sampling stage to the external circuitry and reduce the average input current. They make the input current more signal independent. 
 
 The net effect of the precharge buffers is to reduce both the average current into the analog input pins, and to reduce the amplitude of the "kick" that the external amplifier experiences. Both of these effects lead to an input current and voltage profile which is less dependent on the signal, and therefore leads to less distortion introduced at the input stage. 
 precharge

Question 9

AD7768 FAQ - The input seems to be switching faster than the 256 kSPS rate?

Accepted Answer

The analog input seems to be switching faster than the 256 kSPS output data rate, is this correct? 
 This is a common question for sigma delta ADC architectures like the AD7768 (and the AD7768-4, AD7761, and AD7768-1 New ) 
 The short answer is "Yes". 
 The &Sigma;-&Delta; converter is an oversampled architecture, so the actual sampling rate at the analog inputs, that is the rate at which the input sampling switches are opened and closed, is much higher than the ADC output data rate. On the AD7768 the analog input is sampled at twice the modulator clock frequency, fMOD, which is derived from MCLK. The modulator clock frequency is determined by selecting one of three clock divider settings: MCLK/4, MCLK/8, or MCLK/32. 
 For example, when provided with a 32MHz MCLK, and fMOD is MCLK/4 = 8.192 MHz, the analog input switches are switching at a rate of 2 x 8.192 MHz = 16.384 MHz. In this case the data is oversampled by at least 32x, so the maximum output data rate is 8.192 MHz / 32 = 256 kSPS.

Question 10

AD7768/AD7768-4 FAQ - Clock Selection

Accepted Answer

The AD7768/AD7768-4 MCLK can be applied by using one of the three different options that are available to the user. The purpose of this document is to further explain these three options and how they are configured. The three options are: external CMOS clock, crystal oscillator or LVDS clock. 
 The initial power up of the AD7768/AD7768-4 uses an internal oscillator to set up the device. The clock control is then transferred to an external clock which is valid between 1.15 MHz and 32 MHz. (The maximum crystal frequency from the datasheet is 34 MHz) If the externally applied clock is not detected or an error occurs, then the Device Status register (Register 0x09) will log this error by setting the clock error bit to a one. 
 CMOS Clock 
 To select the CMOS clock option the following conditions must be met: 
 
 CLK_SEL (Pin 58) must be set to zero. 
 Connect XTAL1 (Pin 31) to DGND. 
 The CMOS clock is applied to pin 32. 
 The CMOS logic level in this case is between IOVDD and DGND. 
 
 Crystal 
 In order to use an external crystal it is necessary to adhere to the following steps: 
 
 Channel four of the ADC must be enabled. This is because channel four is linked to the crystal excitation circuitry. Powering down this channel also powers down the crystal excitation circuitry. 
 The CLK_SEL pin must be set to a logic 1. 
 The crystal is applied between pins 31 and 32. Capacitance of approximately 20pF is required on each of these pins. This may vary depending on the crystal that is selected. 
 If the AD7768/AD7768-4 is in SPI control mode then the FILTER/GPIO4 pin (Pin 11) must be set to a logic one. 
 
 LVDS Clock 
 The LVDS clock option is available only in SPI control mode. The following steps must be carried out to enable LVDS clocking to be used: 
 
 Set the CLK_SEL pin to be a logic 1 
 Set the FILTER/GPIO4 pin (Pin 11) to logic 0. This will disable the crystal excitation circuitry. 
 Power up the AD7768 with no external clock applied. Initially it will run off the internal clock for SPI writes until all of the below steps have been carried out. 
 Enable this option by writing to the LVDS_Enable bit (Bit 3) in the Power_Mode register (Register 0x04) 
 Apply the LVDS signals on pins 31 and 32. 
 
 For further information please consult the product datasheet. 
 http://www.analog.com/media/en/technical-documentation/data-sheets/AD7768-7768-4.pdf 
 The AD7768/AD7768-4 evaluation boards allow the user the option to set the MCLK to one of the three options discussed above. The CMOS clock is enabled on these evaluation boards by default. For more information please see the products' evaluation board web page. 
 EVAL-AD7768 Evaluation Board | Analog Devices

Question 11

AD7768 FAQ - What is the maximum input common-mode voltage?

Accepted Answer

Some architectures of ADC require that the input common-mode voltage of the applied analog signal be within a certain specified range, which is often close to the midpoint of the analog input range. 
 On the AD7768, AD7768-4, AD7761, and AD7768-1 New datasheets the input common-mode voltage range is equal to the supply rails, meaning that there is no specific restriction on the input common-mode voltage. The only restriction is that the absolute input voltages on each of the analog input pins should never exceed the AVDD1 supply voltage or go below the AVSS supply voltage.

Question 12

AD7768 FAQ - What is a SYNC and when is it required?

Accepted Answer

The SYNC command on the AD7768 can be thought of as a reset of the digital filter paths and logic within the AD7768. One of the major events that the sync triggers is the reloading of the digital filter coefficients based on the selected configuration. 
 A SYNC should be provided to the AD7768 after any changes to the AD7768 configuration, before valid samples are acquired. 
 The sync signal can be provided direct to the AD7768 SYNC_IN pin, to the START pin, or can be triggered over SPI, under software control. 
 To provide the SYNC over SPI or through the START pin, the SYNC_OUT and SYNC_IN pins must be tied together. 
 Once the SYNC is provided, it is no longer required to provide a SYNC again, until either the part is reset, or the configuration is changed.

Question 13

AD7768: EVB Source Code

Accepted Answer

Question: 
 I want to test more function(and performance) with AD7768 EVB and need to modify its code, 
 Does ADI can provide the AD7768 EVB Source Code and EVAL-SDP-CB1Z protocal to us? 
 Thanks. 
 I also have this question. 
 I have the AD7768 Eval board ( EVAL-AD7768FMCZ ) and the corresponding demo/usb adapter board ( EVAL-SDP-CH1Z ). 
 Using the available AD7768 Evaluation Software (Labview-based example program), I can get the the AD7768 to capture and return data. 
 But, I need to exercise the AD7768 a bit more as part of an early investigation of it's capabilities before the project moves into the next phase. 
 Specifically, I am trying to capture & retrieve data over an extended period of time, say hours to days. I need to do this to verify operation and statistics of the noise. 
 At this point of the project, I cannot justify creating a PCB layout to drive the eval board or re-layout an entire design around the AD7768. 
 I am a bit confused by the parent question, as the date is in 2014 and I'm pretty sure the AD7768 was released June 2016. 
 Hi Jake, 
 We don't usually support this sort of request as ADI would not provide or offer support for the source code. We are planning on releasing new evaluation software and one of the features we would like to include in this new software would be the ability to capture data over a longer period of time. 
 Regarding the original question it is a little confusing for me too. One of the reasons it was not picked up would be the fact there would have been no alerts set up for the AD7768 at that time. 
 Regards 
 Niall 
 Niall, 
 Thanks for the reply and information. 
 Any guess on a release date for the updated Eval SW for the AD7768? 
 Is there a place I can monitor the status? 
 Regards, 
 Jake 
 Hi Jake, 
 Sorry for my delayed response. I would expect we will have this available in the coming weeks - I will try and give you a better estimate once it is known. We are currently estimating and decided what improvements to implement. 
 So the best place to monitor the status would be here - I will keep you posted. 
 Regards 
 Niall 
 NiallM, 
 Any change or update in the status of the improvements to the AD7768 Evaluation SW? 
 Thanks, 
 Jake P 
 Hi Jake, 
 We aim to release an updated version of the software at the end of the month, with some bug fixes and improvements. 
 As of now this doesn't have the functionality you were asking about, to capture data over a longer period of time. This will require an edit to the firmware used and so requires a different resource on our side. I will try to keep you updated once I know more. 
 Do you have a particular duration for which you need to sample continuously? Or could you sample a few minutes worth of data at regular intervals to check the drift in your system? Hours worth of data from the AD7768 will take up an enormous amount of disk space. 
 Regards 
 Niall 
 This document was generated from the following discussion: AD7768 EVB Source Code

Question 14

Synchronising multiple AD7768's to achieve simultaneous sampling of more than 8 channels

Accepted Answer

The AD7768 is an 8-channel, simultaneous sampling &Sigma;-&Delta; analog-to-digital converter (ADC) with a &Sigma;-&Delta; modulator and digital filter per channel, enabling synchronized sampling of ac and dc signals. The AD7768 achieves 108 dB dynamic range at a maximum input bandwidth of 110.8 kHz, combined with typical performance of &plusmn;2 ppm integral nonlinearity (INL), &plusmn;50 &mu;V offset error, and &plusmn;30 ppm gain error. 
 
 The AD7768 also allows synchronized sampling to be extended across multiple AD7768 devices, which enables the user to synchronize sampling across many more channels within the system. For example, a user wishing to simultaneously sample up to 24 channels can easily synchronize across three AD7768 devices. 
 
 The AD7768 offers three options to allow ease of system synchronization. Choosing between the options depends on the system, but comes down to whether the user can supply a synchronization pulse that is truly synchronous with the base MCLK signal. 
 If the user cannot provide a signal that is synchronous to the base MCLK signal, one of the following two methods can be employed: 
 
 Apply a START pulse to the first AD7768 device. The first AD7768 samples the asynchronous START pulse and generates a pulse on SYNC_OUT of the first device related to the base MCLK signal for distribution locally. 
 Use synchronization over SPI (only available in SPI control mode) to write a synchronization command to the first AD7768 device. Similarly to the START pin method, the SPI sync generates a pulse on SYNC_OUT of the first device related to the base MCLK signal for distribution locally. 
 
 In both cases, route the SYNC_OUT pin of the first device to the SYNC_IN pin of that same device and to the SYNC_IN pins of all other devices that are to be synchronized. The SYNC_OUT pins of the other devices must remain open circuit. Tie all unused START pins to a Logic 1 through pull-up resistors. 
 If the user can provide a signal that is synchronous to the base MCLK, this signal can be applied directly to the SYNC_IN pin. Route the signal from a star point and connect it directly to the SYNC_IN pin of each AD7768 device. The signal is sampled on the rising MCLK edge; setup and hold times are associated with the SYNC_IN input are relative to the AD7768 MCLK rising edge. 
 In this case, tie the START pin Logic 1 through a pull-up resistor; SYNC_OUT is not used and can remain open circuit. 
 
 For more information search for AD7768 at: Search | Analog Devices

Popular Forums

Product Forums

Application Forums

Design Center Forums

Highlighted Webinar

Places

Libraries

Upcoming Learning & Events

Challenge Yourself!

What's Brewing

Places

Resources

Visit ContentZone

The Latest Read

New Release

Recent Technical Insights

Products Mentioned

Associated Drivers

Associated Drivers

AD7768: FAQ