The DCLK frequency must be configured in a such way that the data is completely shifted out before a new conversion is completed.
The DCLK is derived from MCLK and is set up by selecting the DCLKxRatio which divides the MCLK frequency by a predefined value.
The minimum DCLK can be calculated as follows:
In High Power mode:
In Low Power mode:
DCLK_MIN_RATIO = minimum clock divider
N = decimation
MCLK = Master clock
DCLK= Output data clock
NDATA_CHANEL = number of data channels being output per DOUT line: 2, 4 or 8.
ODR = Output data rate
Example:
