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Documents Q10. On the AD4111/AD4112/AD4114/AD4115 what’s the equivalent TUE (total uncompensated error) spec across different input voltage ranges for example ±10V, ±5V, ±2.5V or 0-10V, 0-5V, 0-2.5V?
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Products Mentioned

AD4114 Recommended for New Designs
The AD4114 is a low power, low noise, 24-bit, sigma-delta (Σ-Δ) analog-to-digital converter (ADC) that integrates an analog front end (AFE) for eight...
Datasheet
AD4114 on Analog.com

AD4112 Recommended for New Designs
The AD4112 is a low power, low noise, 24-bit, sigma-delta (Σ-Δ) analog-to-digital converter (ADC) that integrates an analog front end (AFE) for fully...
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AD4112 on Analog.com

AD4111 Recommended for New Designs
The AD4111 is a low power, low noise, 24-bit, sigma-delta (Σ-Δ) analog-to-digital converter (ADC) that integrates an analog front end (AFE) for fully...
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AD4111 on Analog.com

AD4115 Recommended for New Designs
The AD4115 is a low power, low noise, 24-bit, sigma-delta (Σ-Δ) analog-to-digital converter (ADC) that integrates an analog front end (AFE) for eight...
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    • Q1. What is the difference between the AD4111/AD4112/AD4114/AD4115?
    • Q10. On the AD4111/AD4112/AD4114/AD4115 what’s the equivalent TUE (total uncompensated error) spec across different input voltage ranges for example ±10V, ±5V, ±2.5V or 0-10V, 0-5V, 0-2.5V?
    • Q11. What is the difference in output data rate between multiple channel configuration and single channel configurations for AD4111/AD4112/AD4114/AD4115?
    • Q12. What is the SPI mode of operation of the AD4111/AD4112/AD4114/AD4115, what polarity do I need to consider?
    • Q13. Where can I find a full and workable sample code for AD4111/AD4112/AD4114/AD4115 for a ST processor?
    • Q14. What is the recommended initialization and register configuration sequence for AD4111/AD4112/AD4114/AD4115?
    • Q15. How many data registers does the AD4111/AD4112/AD4114/AD4115 have to store conversion results for each channel?
    • Q16. What are the General Purpose Input voltage threshold for AD4114, AD4115?
    • Q2. On the AD4111/AD4112/AD4114/AD4115 can I detect if the input signals are floating due to faulty wiring?
    • Q3. What is the recommended anti-aliasing filter required for the AD4111/AD4112/AD4114/AD4115?
    • Q4. Will the same anti alias filter work for both voltage and current inputs of AD4111/AD4112?
    • Q5. Why are the onboard Analog input buffers not required for current measurements AD4111/AD4112?
    • Q6. Can the AD4111/AD41112 current channels accept a bipolar (±20mA) inputs?
    • Q7. What is the AD4111/AD41112 current channel's common-mode input?
    • Q8. Why are the Analog input buffers required for voltage measurements AD4111/AD4112/AD4114/AD4115?
    • Q9. What’s the equivalent input impedance for a pair of voltage input pins of AD4111/AD4112/AD4114/AD4115?
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Q10. On the AD4111/AD4112/AD4114/AD4115 what’s the equivalent TUE (total uncompensated error) spec across different input voltage ranges for example ±10V, ±5V, ±2.5V or 0-10V, 0-5V, 0-2.5V?

Q10. On the AD4111/AD4112/AD4114/AD4115 what’s the equivalent TUE (total uncompensated error) spec across different input voltage ranges for example ±10V, ±5V, ±2.5V or 0-10V, 0-5V, 0-2.5V?

AD4111/AD41112/AD4114/AD4115 are specified for a TUE spec at ±10V full scale range. When input span is reduced the error will change as TUE is specified as a percentage of Full-scale range (%FSR).

In order to calculate the equivalent TUE spec for smaller ranges, we would take the assumption that gain-error and offset error both account for 50% of the total TUE. Please take note that this method provides only an estimated value, the actual performance could be better or worse as we only guaranteed the TUE spec at ±10V input range.

We can start by working through the errors in mV or V initially and then translating to a final TUE Specification

If we take an input span of ±10V and take the TUE from the datasheet specification for ±10V input at 25°C.

For AD4111/AD4112, TUE specs at 25°C is 0.06% Thus,

Offset error = 0.03% of 20V span =>6mV

Full-Scale error at +10V (after correcting for offset error) = 0.03% of 20V span =>6mV

TUE = (6mV+6mV)/20 *100 = 0.06%

For AD4114/AD4115, TUE specs at 25°C is specified as 0.07%. Taking the same steps as above will give you

Offset error = 0.035% of 20V span =>7mV

Full-Scale error at +10V (after correcting for offset error) = 0.035% of 20V span =>7mV

TUE = (7mV+7mV)/20 *100 = 0.07%

Table 2 shows the TUE estimation at 25°C across different ranges. The same approach can be applied when calculating TUE across different temperature.

Table 2. AD411x TUE estimation at 25°C

Input span

AD4111/AD4112

AD4114/AD4115

 

±5V

 Offset error = 6mV;

 Full-Scale error = 6mV*(5V/10V) = 3mV;

 TUE = (6mV + 3mV)/10 *100 = 0.09%

 Offset error = 7mV;

 Full-Scale error = 7mV*(5V/10V) = 3.5mV;

 TUE = (7mV + 3.5mV)/10 *100 = 0.105%

 

±2.5V

 Offset error = 6mV;

 Full-Scale error = 6mV*(2.5V/10V) = 1.5mV;

 TUE = (6mV + 1.5mV)/5 *100 = 0.15%

 Offset error = 7mV;

 Full-Scale error = 7mV*(2.5V/10V) = 1.75mV;

 TUE = (7mV + 1.75mV)/5 *100 = 0.175%

 

0 – 10 V

 Offset error = 6mV;

 Full-Scale error = 6mV*(10V/10V) = 6mV;

 TUE = (6mV + 6mV)/10 *100 = 0.12%

 

 Offset error = 7mV;

 Full-Scale error = 7mV*(10V/10V) = 7mV;

 TUE = (7mV + 7mV)/10 *100 = 0.14%

 

0 – 5 V

 Offset error = 6mV;

 Full-Scale error = 6mV*(5V/10V) = 3mV;

 TUE = (6mV + 3mV)/5 *100 = 0.18%

 Offset error = 7mV;

 Full-Scale error = 7mV*(5V/10V) = 3.5mV;

 TUE = (7mV + 3.5mV)/5 *100 = 0.21%

 

0 – 2.5 V

 Offset error = 6mV;

 Full-Scale error = 6mV*(2.5V/10V) = 1.5mV;

 TUE = (6mV + 1.5mV)/2.5 *100 = 0.3%

 Offset error = 7mV;

 Full-Scale error = 7mV*(2.5V/10V) = 1.75mV;

 TUE = (7mV + 1.75mV)/2.5 *100 = 0.35%

Tags: AD4115 full range AD4111 AD4114 total uncompensated error tue temperature ad4112 Show More
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