The architecture of AD7134 offers excellent attenuation of out of band high frequencies providing 102 dB inherent Alias rejection which caters for most of the application requirements.
Along with the inbuilt Digital filter and decimation all the out of band tones are rejected.
Also note that the front-end circuits will also have some level of attenuation for out of band high frequencies, making the requirement for anti-alias filter redundant. If the rejection ask is more then 102dB + front end rejection, then we will need a filter.
The input range of the AD7134 is +/-Vref, this means that if a 4.096V reference is used, then the input signal can swing 8.192V pkpk. The AD7134 has 4 differential input channels and each channel expects a fully differential signal, and for best performance this should be centered around a common mode voltage that can be anywhere from Vref/2 to 2.5V
VDiff = (VAIN+) - (VAIN-) , where
VDiff – Differential input voltageVAIN+ - Voltage on Positive input
VAIN- - Voltage on Negative input
Differential input voltage equals (VAIN+) - (VAIN-) as shown in the right side of the below figure.
Left side shows the swings on the Pins AINX+ and AINX-
For best performance the differential input signal needs to be biased to Vref/2 to 2.5V.
Yes, AD7134 input is resistive based and therefore can be driven directly by any instrumentation amplifier such as the ADA4254 or the LTC6373 or using an operational amplifier.
Q4. What is the difference between Master and Slave mode? Which one should I use for my application?
When the AD7134 is operating in master mode the output data rate (ODR) and DCLK are
generated by AD7134 therefore the digital host does not need to take any action in relation to the generation of the ODR or DCLK
signals and just needs to sample data. For some of the ODR values dynamically changing the ODR signal is faster when operating in master mode.
When slave mode is selected the ODR and DCLK both need to be provided by digital host.
This mode is best suited when multiple channels across AD7134 devices need. Therefore, when the data is required to be sampled simultaneously from all channels of different AD7134 devices that are operating at the same ODR, then the Slave mode is the best option
On the AD7134 there are 5 different digital filters that enable the AD7134 to be used in various application requirements.
On the AD7134 the filters available are
are two variants of flat passband brick wall FIR filter, two variants of low latency SINC3 filter and SINC6. Brick wall FIR filter response is needed for applications such as data acquisition or SONAR or Electronic test and measurement. The 32 udB low ripple FIR filter would ensure flat passband and would help user extract all details of the signal.
SINC3 filter would be useful for low latency applications where speed of measurement is important, applications such as control loops or protective relays. The removal of AAF in this alias free AD7134 and the SINC3 low latency filter helps achieve low latency signal chain path.
The SINC3 with 50/60 Hz rejection helps in applications demanding rejection of power line frequency with fast settling at ODR = 50 sps.
Please refer to the Excel based Filter tool on the AD7134 product page
There is an IBIS model available for the AD7134 that can be downloaded from the product web page. – add the link
Discrete time ADCs have a sample and hold circuit at the input. The input signal is converted to a discrete time signal by the sample and hold circuit before quantized. Continuous time ADC does not sample and hold circuit at the input. Sampling is taking place at the quantizer after the sigma delta modulator.
Please refer this article AC and DC Data Acquisition Signal Chains Made Easy for more details
Q8. Is there a relationship between the power and output data rate, i.e. does power go down as you decrease the output data rate?
Power does not scale with the output data rate as it does for Discrete time ADC’s although it reduces marginally. so, for SINC3 filter ODR=1.5Msps the power is 111mW and for 10 sps it is 96mW.
Please refer to datasheet plots for more details
Overall group delay is total latency added by the ADC. This delay includes the delays from the point of sampling to the digital filter output. The internal delays that contribute to this spec include Modulator, ASRC, Digital filter group delay and Digital interface Delay.
There are several diagnostics available on the AD7134, that enable the monitoring of the different functional blocks on chip. Examples of these include Internal Fuses, Analog input over range, MCLK frequency check, SPI communication, Memory map, ODR input frequency, Digital Filters and reports error to the users via register flags which can be accessed using SPI. Additionally, there is also an option report the errors on the GPIO pins
The full list of diagnostics can be found in the datasheet.
Yes. Each time that CS is taken high, the serial interface is reset. When CS is taken low, the serial interface is in a state where it expects a write to the communications register, indicating the next operation. This feature is useful as it allows the user to frame the commands
Its recommended to tie all the grounds together to a single large plane. The AD7134 evaluation board runs with a Switch mode power supply with the analog and digital supplies shorted together. Please refer to the board drawings in the Evaluation board user guide
When reading or writing to the AD7134, a user can transmit the data as a continuous stream mode. This helps in reducing the time to configure the part. Please see the Stream mode section in the Data sheet.
The AD7134 accepts truly differential signals centered around 2V to 2.5V(Common mode) therefore if your signal is at this level you don’t need to do anything, if however you signal is single ended or not centered around 2V to 2.5V then you will need some up front signal conditioning to bring the signal in line to the expected levels. Please refer to front end applications in the Data sheet.
The integrated ASRC of the AD7134 helps achieve multidevice synchronization with a single low speed ODR line. The phase matching between channels is less than 10 ns typically of making it easy to synchronize multiple devices.
To achieve tight synchronization, slave mode is recommended, here the devices should be configured with gated DCLK and all the ODR and DCLK signals of different devices should be shorted together. The SPI must then be used to set the DIG_IF_RESET bit, this ensure the digital interface is reset before the data capture begins. This DIG_IF_RESET command must be given to all the slaves simultaneously using one single SPI write command.
On the AD134 twos complement coding is used to represent both negative and positive differential voltages applied to the analog inputs of the ADC.
The input range is from negative Full Scale (-VREF) to positive Full Scale (+VREF). The output coding is
- A negative full-scale voltage applied to the Analog inputs results in an output code of (0x800000). Negative value have the MSB set to 1 Always
- à Midscale zero differential input voltage applied to the analog inputs results in an output of 000...000 (0x000000)
- A positive full-scale input voltage applied to the Analog inputs results in an output code of 0111...111 (0x7FFFFF), positive values have the MSB cleared Always
Please refer to Datasheet table 26
ADC conversions are not linked to ODR high or low state, the AD7134 has an ASRC (asynchronous sample rate converter) on board, this is located In between, and conversion happens in modulator. ASRC resamples the data as shown in the figure below
Q18. Can i configure different channels with different digital filters and different Output Data Rates?
Yes, Different channels can be programmed with different filters in the SPI control mode.
Different channels can have different ODR rates limited to ODR, ODR/2, ODR/4 and ODR/8
AD7134 has Flexible digital interface options allowing customers to connect with Free clock-based modes like SPORT or Gated clock interface modes like FPGA or SPI
Depending on the performance needed for the end application we can choose the power mode
Both the high-performance mode and Low power mode supports the entire output data range of 10 SPS to 1.5 MSPS with low power mode having some degradation in performance
Please refer to Tables 9 to 16 in data sheet
In master mode, the ODR_VAL_INT_x and ODR_VAL_FLT_x registers need this implementation. When this bit is set, multiple bytes of data that have been transferred using the SPI are written at one time to the slave. Upon completion of the transfer, the slave device clears this bit (auto clear),
So you write these registers and then set the master slave transfer bit to update the ODR value.
Q22. My application require digital isolation. What are the minimum number of digital lines required to interface with the AD7134?
The AD7134 has a Minimal I/O mode, this mode helps achieve full control of the AD7134 using just 4 signals that encompass the control and data lines. The measurement data from all 4 channels is serialized on one DOUT line of the AD7134, the SPI clock and data clock are shared on same wire. For more details on the Minimum I/O mode please refer to the datasheet page 64.
Another option would be to use PIN Mode, using PIN mode on the AD7134 eliminates the need for SPI communication interface to control the AD7134. The AD7134 is configured by HW pins that are pulled either high or low allowing user to access data for a fixed configuration
For more details, please check the AD7134 Product Page.