The end application will dictate the power mode to use.
Common applications for the part are smart transmitters, process control input modules and low power or battery operated instrumentation.
For Field transmitter applications, the maximum current that can be used by the complete transmitter is 4 mA when the transmitter is loop powered. Therefore, the less current consumed by the ADC, the better, as it allows more current for the processor, and other components in the design. Therefore, the AD7124-4/AD7124-8 for this application would be used in low power mode.
For process control, current consumption is not a concern so any power mode could be used. The benefits of using the full power mode for this application is that for a given output data rate, the rms noise is lowest in the full power mode. Also, the part supports higher output data rates in the full power mode. This enables the customer to increase the number of channels sampled per second for a given level of performance.
There are a number of key differences between the standard parts and the B-grade parts, and the choice of part for your application will depend on your requirements. The key differences are
B-Grade v’s Standard Package:
The B-grade is available in the LFCSP package only whereas the standard is available in both TSSOP and LFCSP. The LFCSP package is 5 x 5 mm package for both B-grade and standard however the height is the key difference, the B-grade height is 0.95 mm and the standard is 0.75mm.
B-Grade v’s Standard Internal Reference TempCo:
The B-grade AD7124-4/8 internal reference has a tempco of 10 ppm/’C max, whereas the standard silicon (LFCSP) has a temp co of 15 ppm/’C max
B-Grade v’s Standard Multichannel settling time (at G=1):
The B-grade silicon includes a pre-charge buffer which aids the settling and hence ensures that all conversions are fully settled within the allowed time.
The standard silicon, when used in multi-channel mode, does not settle within the allowed time when switching channels for gains of 1 when high output data rates are used in conjunction with large resistive loads.
B-Grade v’s Standard Excitation currents status in standby mode:
The excitation currents on the B-Grade can remain active in standby mode. This is useful when current consumption minimization is not important. On the standard silicon (LFCSP and TSSOP), the excitation currents are disabled when the ADC is placed in standby mode.
Some customers use single conversion mode as a timing mechanism to provide conversions within timeslots. In this use case, keeping the excitation currents enabled during standby mode minimizes the power up time.
B-Grade v’s Standard Gain Registers value when MCLK & SCLK are Asynchronous
On the standard silicon, the gain register can reset to its default value periodically if SCLK and MCLK are asynchronous. So, if internal Full Scale (FS) calibrations or system FS calibrations are performed in a system where SCLK and MCLK are asynchronous, the gain register should be read periodically to ensure that it has not reset.
On the B-grade, the gain register does not reset even when SCLK and MCLK are asynchronous.
The B-Grade is better than the standard and should be used for new designs, to understand the key differences see Q2 above.
When ordering there are two options available for each product,
The extra B in the first option for each product represent the B-grade. The B-grade offers substantial improvements over the standard silicon and therefore would be recommended for new design, for full details on the differences Q2 above.
There are 3 power modes available on the AD7124-4/AD7124-8, low, mid and full power mode.
In full power mode the analog input signal is sampled at 614.4 kHz. The maximum output data rate is 19.2 kHz. In this mode, the part has lowest rms noise for a given output data rate. It also has low offset drift and best PSR.
In the mid power and low power modes, the master clock is internally reduced by 4 in the mid power mode and 8 in the low power mode. This means that the sampling frequency of the input signal is also reduced by 4 or 8 accordingly, this also leads to the reduction of current consumption to some of the on board analog circuitry. This saving in current consumption offers considerable savings in the overall power budget, however this reduction in current leads to an increase in the rms noise, and also leads to higher offset drift, PSRR.
There are many digital filters available on the AD7124-4/AD7124-8 these include standard sinc filters, Sinc4, Sinc3 as well as Sinc4+Avgeraging and Sinc3 plus average, as well as post filters that offer simultaneous 50Hz and 60Hz rejection with reasonable settling time.
To highlight the key differences we will give an example. Looking at some of the applications where the AD7124-4/AD7124-8 are used and specifically focusing on industrial applications, 50Hz and 60Hz rejection is one of the key requirements. For these applications customers would like to sequence through multiple channels with each channel producing a valid conversion in 20ms. The main challenge here is the difficulty to achieve this timing while attaining good 50/60Hz rejection.
The post filters on the AD7124-4/AD7124-8 offer a compromise between settling time and rejection.
If we look at a standard sinc3 filter this has a settling time of 60ms when operating at 50sps while still offering simultaneous 50Hz and 60Hz rejection. The rejection obtained by this filter is 66dB
There are a number of different options available for the post filters, if we take the 25sps post filter. This filter has a settling time of 40ms and has a rejection of 62dB. The rejection is slightly degraded using the post filter when compared with the sinc3 filter, but the value is acceptable for a lot of the applications, the key difference is around the settling time where the post filters settle much faster than the sinc3 filter.
To see the behaviour of the different filter options understand the trade offs and associated timing please go to our virtual eval online simulation tool, you can find this at the following weblinks
Click here to watch a video that uses the Virtual Eval online tool to highlight the filters available.
Yes, the IBIS models are available for the AD7124-4 as well as the AD7124-8. The link to the models can be found on the product pages at the following links
The AD7124-4/AD7124-8 have been designed with a high degree of on board diagnostics. The diagnostics enable a guaranteed and trusted result. Diagnostics are available from the input right to the digital interface and can be enabled/disabled through specified registers in the register map. These diagnostics can be not just used for functional safety type applications but can also be used to give a level of confidence that the measurement solution is working as expected.
The on-chip diagnostics allow the user to verify the circuit connections ensuring that the input signal is still connected as well as carrying out checks on the internal blocks of the chip as the PGA, reference and ADC itself can be monitored. A key benefit is that all the on-chip registers can be monitored, and thus gives the user confidence that no register changes have occurred. The AD7124-4/AD7124-8 also incorporates a high number of diagnostics around the serial interface which include read/write checks, a full list of diagnostics can be found in the datasheet. We also have a video that discusses each of the available diagnostics in detail and this can be found here
Yes. Each time that CS is taken high, the serial interface is reset. When CS is taken low, the serial interface is in a state where it expects a write to the communications register, indicating the next operation. This feature is useful as it allows the user to reset the serial interface.
When reading or writing to the AD7124-8, a user can transmit the data as a continuous stream or the data can be split into bytes. For example, if writing 24 bits to the ADC, all 24 bits can be transmitted continuously or the data can be divided into 8-bit words. However, if the data is divided into bytes, CS must be held low until all bytes are transmitted.
The serial interface is independent of the sampling process. So, once the single conversion is initiated, the AD7124-8 will power up and perform the single conversion irrespective of the polarity. So, the user can take low, initiate the single conversion and then take high again. When the conversion is complete, can be taken low to read the conversion and another single conversion can be started if required.
When is taken high, the DOUT/ pin is tri-stated. Therefore, the DOUT/ pin will not indicate the end of the conversion. The user can determine the end of the conversion by reading the status register. Alternatively, the conversion time could be timed out by the microcontroller clock.
HBM Model Pass Level: 4.0 kV, FICDM Model Pass Level: 1250 V, Machine Model Pass Level: 400 V
Yes, an anti-alias filter is required. However, because the AD7124-4/AD7124-8 is a sigma delta ADC, this means that the ADC oversamples the analog input, thus greatly simplifying the design of the anti-alias filter when compared to an ADC that samples at the Nyquist rate (Maximum signal Bandwidth * 2).
The AD7124-4 / AD7124-8 also incorporates a digital filter, where the associated frequency response is reflected around the sampling frequency of the ADC. This means that the filter will provide 0dB of attenuation at frequencies which are integer multiples of the ADC sampling frequency. Thus the purpose of the an anti-alias filter is required to provide adequate rejection at multiples of the ADC sampling frequency. The anti alias filter is usually a single pole (possibly a 2 pole) RC filter is all that is required. An example of an anti filter for the AD7124-4/AD7124-8 would be a 1KΩ resistor in series with each analog input, a 0.1μF capacitor from AINP to AINM, and a 0.01 μF capacitor from each analog input pin to AVSS. These R and C values are recommended when the analog input channel is buffered.
When the converter is operated in unbuffered mode (gain = 1), the inputs look directly into the sampling capacitor of the modulator. The modulator is continually charging and discharging the sampling capacitor. If the time constant of the anti-aliasing filter is too large, the modulator may be unable to fully charge the sampling capacitor and gain errors will result. To prevent the R-C combination from introducing errors, the R and C values used must be limited.
A single microcontroller can be used to communicate with several AD7124-4/AD7124-8 devices. The input of the ADC can be used to enable or disable the serial interface to the associated ADC. By controlling the inputs to the ADCs using a decoder, the microcontroller can communicate with each ADC individually or simultaneously.
The figure below shows the interface between a microprocessor and several ADCs. The input of each ADC is connected to the decoder. Using the decoder, the microprocessor can select the ADC with which it wants to transfer data/instructions. When is high, the serial interface of the ADC is disabled and it ignores any activity on the data bus. To communicate with the ADC, its line can be taken low. The ADC will then have access to the data bus between itself and the microprocessor. The datasheet should be consulted for timing specifications.
On the AD124-4 & AD7124-8 two different coding options exist unipolar and bipolar coding. Unipolar coding is used to represent positive voltages only, and bipolar coding can be used to represent both negative and positive differential voltages applied to the analog inputs of the ADC.
For the ADC operating in unipolar mode, the input range to the ADC is from 0V to Full scale, where the full scale value is equal to VREF/Gain (reference input voltage/ selected PGA gain). The output coding is straight binary which means that
When the ADC is operated In bipolar mode, the input range is from negative Full Scale to positive Full Scale where Full Scale is VREF/Gain (reference input voltage/selected PGA gain). The output coding for bipolar operation is offset binary with
As discussed in Q16 above, the ADCs operate in unipolar or bipolar coding modes.
When unipolar mode is selected the ADC output code for any analog input voltage applied to the analog inputs can be calculated using the following formula as:
Code = (2^N × AIN x Gain)/VREF
Working through an example where:
AIN = 1V, VREF=2.5V, PGA = 1.
The equivalent code in unipolar mode is
Code = (2^N × AIN xGain)/VREF = (2^24 x 1V x 1)/2.5V = 6710886
When bipolar mode is selected the ADC output code for any analog input voltage applied to the analog inputs can be calculated using the following formula as:
Code = 2^ (N – 1) × [(AIN x Gain/VREF) + 1]
AIN = 1V, VREF=2.5V, PGA=1. The equivalent code in bipolar mode is
Code = 2^ (N – 1) × [(AIN/VREF) + 1] = 2^ (24 – 1) × [(1V x 1/2.5V) + 1] = 11744051
The following equations show the calculations associated with the offset and gain for both unipolar and bipolar modes of operation. Note that the AD7124 ADC does all this processing internally, therefore the main conversion of codes to associated voltages can be found described in Q17.
Data = [(0.75 × VIN x Gain/VREF) × (2^23) – (Offset_Reg – 0x800000)] × Gain_Reg/0x400000 × 2;
Data = [(0.75 × VIN x Gain/VREF) × (2^23) – (Offset_Reg – 0x800000)]× Gain_Reg/0x400000 + 0x800000;
Some additional notes:
The 0.75 number reflects the attenuation of the analog input to 75% before the offset and gain coefficients are applied. This is done to avoid modulator saturation after applying the offset and gain corrections. This number will vary slightly from part to part because of manufacturing tolerances.
The value 0x800000 is the default offset coefficient. In the Offset_Reg each bit is equal to 1LSB.
The additional 0x800000 in the bipolar equation is to implement the offset binary that is used in bipolar mode.
The 0x400000 along with the gain coefficient invert the 0.75 scaling.
Working through an example where we assume there is no offset and no gain correction applied to the ADC output codes, where the offset coefficient of 0x800000 and gain coefficient of 0x555555. The offset correction is 0x800000– 0x800000= 0. The gain coefficient of 0x555555 divided by the fixed value 0x400000 together give a value closer to 1/0.75. So, the attenuation (0.75) is reverted here.
For AD7124-4/AD7124-8 the sensitivity of the internal temperature sensor is 13,584 codes/°C, approximately when Vref = 2.5V. Both unipolar and bipolar coding can be used when reading the internal temperature sensor.
The formula to convert the ADC output code to a temperature when operating in unipolar mode is:
Temp (°C) = (Conversion / (2*13,584)) – 272.5
ADC is configured in unipolar. The output code of the AD7124 internal temp sensor at ambient temperature is 8082480 this code to a temperature is done as follows
Substitute Conversion = 8082480,
Temp (°C) = (8082480/ (2*13,584)) – 272.5 = 25°C
Yes, you can share AIN and IOUT in a single pin and the number of AIN pins per sensors is minimized. However, sharing pins will add error to the overall conversion as there will be a voltage drop across the R of the RC anti-aliasing filter/EMC filtering which in series with the RTD, thus limited R values can be used. It is recommended for EMC/anti-aliasing optimum performance; it is a good practice to enable IOUT on a dedicated pin and applied to the RTD outside of the AIN input filters. In this case, only leakage current goes through the R value of the external filter so the impact of the R value on overall accuracy is minimize. This implementation uses one extra AIN pin versus the shared implementation.
Yes, Vbias can be brought out to AINM pin. However, if there are large RC values connected to AINM then AINP sees a filtered version of the bias voltage. The difference between the bias voltage at AINP and AINM results in a voltage error that can be detected by the ADC, so it adds an error to the measurements. To use a shared pin approach, limited RC values must be use. To use unlimited RC values, it is recommended to use a dedicated pin for Vbias and applied Vbias as the common mode voltage on the outer side of the anti-aliasing filter.
We share the DOUT and RDY pins to reduce the pin count. Sharing DOUT and RDY has some other benefits also. If isolation is used between the ADC and the uC, having a shared DOUT/RDY line reduces the number of isolation channels needed. To know when a conversion is ready, /CS can be taken low and the DOUT/RDY pin can be monitored. Alternatively, the RDY bit in the status register can be monitored.
For a system that uses multiple ADCs, the interface can be simplified by synching the devices. For example, configure one ADC as the master and configure the remaining ADCs as slaves. The clock from the master device can then be used as the clock for all parts. Writing a common command to all devices such as selecting continuous conversion mode will reset all ADCs. The customer would then only need to monitor the DRDY signal from the master device. When the master DRDY goes low, read its conversion. At this point, the other ADCs will also have conversions available so their DRDY signals do not need to be monitored. This architecture would simplify the connections between the ADCs and the uC. With this architecture, it is important that all conversions from the ADCs are read back before the next conversion from the master ADC is ready this ensures that all conversions from ADCs are read (ensures no conversions are missed)
To ensure synchronization between multiple AD7124-4/AD7124-8 devices, the same master clock must be used for all devices. If the AD7124 internal clock has been used, then one ADC serves as the master and uses its own internal clock and this clock is made available on the device CLK pin. This clock is used as the external clock source for other ADCs. To synchronize the sampling instant /SYNC pin can be used to control the start of conversion alternatively a common command such as enabling continuous conversion will reset the conversion process at all parts. It will only have the 1MCLK uncertainty between conversions of different devices.
For a system that requires multiple channels, one AD7124-8 can support up to 8 differential/15 single ended input channels and one AD7124-4 can support up to 4 differential/7 single ended input channels. If the system requires a greater number of channels, either a single ADC with an external MUX can be used to increase the channel count as shown in (Figure 1) or, multiple ADCs can be used (Figure 2).
Figure 1. 32 Channels using MUX and single AD7124-8
Figure 1 shows an example for 32 Analog input channels using a single AD7124-8. Here, 4 8x1 muxes (ADG707) are connected to 4 of the ADC’s Analog input channels, thus supporting 32 differential inputs. The multiplexer logic pins can be controlled via the AD7124-8’s general-purpose output pins. This option simplifies the Analog front-end circuitry and digital software interface. However, converting multiple ADC channels will take time. At Full power mode 50/60Hz rejection (FIR 25sps) the throughput time for 32 channels is 41.72ms x 32 = 1.34s.
If the system requires faster measurement speed, it is recommended to use multiple AD7124-4/AD7124-8 devices. Figure 2 shows the connections for 4 AD7124-8s which support 32 channels in total. In this mode, the measurement speed will increase by the number of ADCs used. So for the same scenario as above, the throughput time for 32 channels will be reduced to 1.34s/4 = 0.335s. The ADCs can be synchronized so that a common SPI bus can be used by all the ADCs. Synchronisation ensures that the conversions are available from each ADC at the same time, ensuring that all data is captured correctly. For more details please see below threads.
Figure 2. 32 Channels using multiple AD7124-8
Long Term Drift (ppm/1000hrs)
The table shows the Internal reference long term drift over 1000 hours for the TSSOP package (standard AD7124-4 silicon), 0.75mm LFCSP package (standard AD7124-4 and AD7124-8 silicon) and the 0.95mm LFCSP package (B-grade AD7124-4B and the AD7124-8B silicon).
To measure the drift, parts were tested in an oil bath after being soldered to the PCB. Post solder, the internal reference was monitored for 1200 hours with the oil temperature maintained at 25’C. To allow some time for the package to de-stress post soldering, the first 200 hours of data is ignored. So, the table shows the internal reference drift with time for the 200 hours to the 1200 hours period.
Baking parts post soldering allows a package to de-stress faster. To confirm this, the standard silicon (TSSOP and 0.75mm package) were tested with a bake included. So, post soldering to the test board, the PCB was baked (placed in an oven) at 85C for 3hrs. Following this bake time, the boards were placed in the oil bath and the internal reference was again monitored for 1200 hours with the oil bath held at 25’C. The table indicates the results for the 200 hours to 1200 hours duration. It can be seen that the bake enables the package to de-stress quicker, leading to a better long-term drift (over 1000 hours) specification.
Note that the key thing to observe from the table is that all results show that the reference voltage is always within the datasheet initial spec of 0.2%.