FAQ: How are the offset and gain coefficients applied to the data conversion of AD7124-4/AD7124-8?
The following equations show the calculations associated with the offset and gain for both unipolar and bipolar modes of operation. Note that the AD7124 ADC does all this processing internally, therefore the main conversion of codes to associated voltages can be found described in How to convert the AD7124-4/AD7124-8 data output Code to equivalent analog input voltage?
Data = [(0.75 × VIN x Gain/VREF) × (2^23) – (Offset_Reg – 0x800000)] × Gain_Reg/0x400000 × 2;
Data = [(0.75 × VIN x Gain/VREF) × (2^23) – (Offset_Reg – 0x800000)]× Gain_Reg/0x400000 + 0x800000;
· Where Data = output code conversion
· VIN= applied analog input voltage, AIN
· VREF= reference voltage
· Offset_Reg = value contained in the offset register
· Gain_Reg = value contained in the gain register
· Gain = PGA gain setting
- The 0.75 number reflects the attenuation of the analog input to 75% before the offset and gain coefficients are applied. This is done to avoid modulator saturation after applying the offset and gain corrections. This number will vary slightly from part to part because of manufacturing tolerances.
- The value 0x800000 is the default offset coefficient. In the Offset_Reg each bit is equal to 1LSB.
- The additional 0x800000 in the bipolar equation is to implement the offset binary that is used in bipolar mode.
- The 0x400000 along with the gain coefficient invert the 0.75 scaling.
If we work through an example here, where we assume there is no offset and no gain correction applied to the ADC output codes, where the offset coefficient of 0x800000 and gain coefficient of 0x555555. The offset correction is 0x800000– 0x800000= 0. The gain coefficient of 0x555555 divided by the fixed value 0x400000 together give a value closer to 1/0.75. So, the attenuation (0.75) is reverted here.