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There are two ways to read the conversion result of the AD7380/AD7381. The conversion result can be read via SDOA and SDOB or via SDOA only . The 2 wire mode allows the conversion result of ADCA via SDOA and the conversion result of ADCB via SDOB. Reading conversion result in 2 wire mode requires 16 SCLK cycles and 14 SCLK cycles for AD7380 and AD7381 respectively. When in 1 wire mode the conversion result of ADC A and ADC B are clocked out in SDOA only and requires 32/28 SCLK cycles for AD7380/AD7381. The one wire mode requires more SCLK cycles that would mean longer time clocking out the conversion result which in effect have a lower throughput rate but the microcontroller will have to interface to only one digital output pin therefore saving pins and complexity. The 2 wire mode requires lesser SCLK cycles which can maximize the throughput rate of the AD7380 but requires two microcontroller I/O pins to read the conversion result.