Q&A - Recent Threads

current measurement problem

lyesbaci — Mon, 13 Apr 2026 09:12:41 GMT

Hello,

We are developing a coulombermeter with AD7705.

AD7705 is used to measure the voltage of a shunt 300A 60 mV and I can have the current with the voltage

Everthing works, the current is small (< 10A), but I can have some peak of current (179.62A ADC value about 0x00A0?).

The peak of current is about each 10mins?

* I send below message to init AD7705

0x20, 0x0C

0x10, 0x68

* we have a 4.9152MHz Crystal Oscillator on MCLK IN and MCLK OUT=AB308-4.9152MHZ with 16pF capacitor

* Reference voltage 1.25V=TLV431BQDBZRQ1

*You find attached the schematic

Do you know where is my problem?

I don't get the test pattern properly in dual LVDS lane mode

MMalmir — Mon, 13 Apr 2026 08:30:26 GMT

I’m currently running some experiments by interfacing an EVAL‑AD4080‑FMC board with a Zedboard. I’ve flashed the latest ADI Kuiper Linux image to the SD card, and I’m using ACE software to capture data from the ADC.

My initial test was to read the test pattern 0xAC5D6, as specified in the datasheet. With the default configuration (single LVDS lane, 40 MSPS, 400 MHz clock) and by setting the INTF_CHK_EN bit in the ADC_DATA_INTF_CONFIG_A register, I can successfully read the correct test pattern

However, I’m unable to get the correct test pattern when switching to two LVDS lanes. For this setup, I wrote 0x54 to the ADC_DATA_INTF_CONFIG_A register and tested LVDS_CNV_CLK_CNT values from 0 to 10 in the ADC_DATA_INTF_CONFIG_B register. The sampling rate remained at 40 MSPS. I repeated the test using both 400 MHz and 200 MHz clocks, but the correct test pattern still does not appear.

Do you know if there is anything I might be missing in the configuration for the dual‑lane mode?

Filter Coefficients

bluespider — Fri, 10 Apr 2026 15:09:56 GMT

Is it possible to have the digital filter coefficients for this ADC?
They are needed for further data processing and this is the only ADC we use that doesn't supply them in the datasheet.

Peak Current of Input Pin

DespicableMe — Fri, 10 Apr 2026 12:42:25 GMT

Hi,

Hi,
For AD4112, as per datasheet, each current input pin can handle max of +-50mA. Is this continuous current?

What is the peak current that each pin can handle and for what duration?

Thanks.

AD7785 Clock Duty Cycle

miky — Thu, 09 Apr 2026 06:06:50 GMT

Hello.

I have a question about AD7785.

The AD7785 datasheet states that the duty cycle for the external clock must be within ±5%.

However, while it notes that “This applies to an external 64 kHz clock; a 128 kHz
clock can have a less stringent duty cycle,” it does not specify the exact conditions.

To what extent can the duty cycle be relaxed when using a 128 kHz clock?

Best regards.

AD5940 (ADICUP3029): Synchronized ECG + ICG (BIA) at 512 Hz Hangs After Initialization

Sadique — Wed, 08 Apr 2026 19:55:33 GMT

Hello ADI Community,

I am developing a combined, synchronized Electrocardiogram (ECG) and Impedance Cardiography (ICG / BIA) application using the EVAL-ADICUP3029 paired with the AD5940 BioZ shield. I am using Keil µVision and the standard AD5940 firmware library (v0.2.1).

My Goal: To achieve a simultaneous ECG and single-frequency (50 kHz) BIA measurement at a 512 Hz Output Data Rate. Because the AD5940 has a single ADC, my strategy is to interleave the measurements using the sequencers:

The Wake-Up Timer (WUPT) runs at 512 Hz and wakes up Sequencer 0 (ECG).
Sequencer 0 configures the ADC for SINC3, takes the ECG measurement, pushes it to the FIFO, and then uses a register write (SEQ_WR) to instantly trigger Sequencer 1 (BIA).
Sequencer 1 configures the switches/DFT, takes the ICG measurement, pushes it to the FIFO, and goes to sleep.

The Issue: The code compiles flawlessly and the SPI communication is verified (the board prints the correct silicon version and library info). However, immediately after starting the applications, the stream stops. No data is ever printed, and polling the FIFO count (AD5940_FIFOGetCnt()) always returns 0.

Here is my terminal output before it hangs:

Plaintext

==================================
ADICUP3029 BOOT SUCCESSFUL!
Mode: Synchronized ECG + ICG
==================================
This AD594x!
Note: Current Silicon is S2
AD5940LIB Version:v0.2.1
Configuring ECG Sequencer...
Configuring BIA Sequencer...
Starting Synchronized Measurements!

Key Setup Details:

1. FIFO Configuration (Routing both sources):

C

  fifo_cfg.FIFOEn = bFALSE;
  fifo_cfg.FIFOMode = FIFOMODE_FIFO;
  fifo_cfg.FIFOSize = FIFOSIZE_4KB;                       
  fifo_cfg.FIFOSrc = FIFOSRC_DFT | FIFOSRC_SINC3; /* Both sources */
  fifo_cfg.FIFOThresh = 8; 
  AD5940_FIFOCfg(&fifo_cfg);                             
  fifo_cfg.FIFOEn = bTRUE;  
  AD5940_FIFOCfg(&fifo_cfg);

2. WUPT Master Timer (Triggering ECG only):

C

  wupt_cfg.WuptEn = bTRUE;
  wupt_cfg.WuptEndSeq = WUPTENDSEQ_A;
  wupt_cfg.WuptOrder[0] = SEQID_0; /* Wake up ECG first */
  wupt_cfg.SeqxSleepTime[SEQID_0] = (uint32_t)(32000.0 / 512.0) - 2 - 1;
  wupt_cfg.SeqxWakeupTime[SEQID_0] = 1; 
  AD5940_WUPTCfg(&wupt_cfg);

3. The Baton Pass (End of ECG Sequence 0):

C

  /* Disable ADC block to prepare for BIA */
  AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_ADCPWR, bFALSE);  
  
  /* Hardware Trigger Sequence 1 (BIA) */
  AD5940_SEQGenInsert(SEQ_WR(0x00002064, 2)); /* Write to REG_AFE_SEQTRG */

  /* Put Sequencer 0 to sleep */
  AD5940_EnterSleepS();

My Questions:

Is writing 2 to REG_AFE_SEQTRG (0x00002064) the correct and reliable way to chain Sequencer 0 to Sequencer 1 within the sequence generator?
When rapidly switching the ADC between SINC3 (for ECG) and DFT (for BIA) at 512 Hz, are there specific ADC/Filter reset or settling commands I must include in the sequences to prevent the ADC from locking up?
Can the FIFO safely handle FIFOSRC_DFT | FIFOSRC_SINC3 multiplexing without halting, or does this mixed-data configuration require a specific word-alignment strategy?

Any insight into why the sequencers are failing to cycle or push data into the FIFO would be massively appreciated! Thank you.

LTC2309 - Residual Charge Question

AlexanderK23 — Tue, 07 Apr 2026 16:17:35 GMT

Hello,

I was wondering if we have control between switching the mux and the read commands through I2C.

Looking to see if there is significant residual charge when switching the internal mux.

Regards,

Alex

LTC2309 - Over Conversion Range

AlexanderK23 — Tue, 07 Apr 2026 16:07:11 GMT

Hello,

I am looking into the LTC2309 over conversion range effects. If I am running in Uni-polar mode, the maximum conversion range is 4.096V.

What do I read on the digital output if I have a 5V analog input? (Assume the ADC is powered also by 5V)

Thank you!

Alex

AD5941 setting Vzero and Vbias

lizziechu — Mon, 06 Apr 2026 01:39:15 GMT

Hi,

I am currently testing AD5941 to create a ramp from -400mV to 1200mV using HSDAC direct code and an external opamp with a gain of 2 for a potentiostat application. The hardware is 1 electrode connect to CE0 and the other electrode connect to SE0.

My setup is currently is this in the code.

extern uint32_t AppBuff[APPBUFF_SIZE];
static const char *TAG = "FSCV_APP";

AppRAMPCfg_Type AppRampCtrl = {
  .bParaChanged = bFALSE,         /**< Indicate to generate sequence again. It's auto cleared by AppBIAInit */
  .SeqStartAddr = 0,              /**< Initialaztion sequence start address in SRAM of AD5940  */
  .MaxSeqLen = 0,                 /**< Limit the maximum sequence.   */
  .SeqStartAddrCal = 0,           
  .MaxSeqLenCal = 0,             

/* Application related parameters */ 
  .LFOSCClkFreq = 32000.0f,         /**< The clock frequency of Wakeup Timer in Hz. Typically it's 32kHz. Leave it here in case we calibrate clock in software method */
  .SysClkFreq = 16000000.0f,           /**< The real frequency of system clock */
  .AdcClkFreq = 16000000.0f,           /**< The real frequency of ADC clock */
  .RcalVal = 10000.0f,              /**< Rcal value in Ohm */
  .ADCRefVolt = 1820.0f,           /**< The real ADC voltage in mV. */
  .bTestFinished = bFALSE,			/**< Variable to indicate ramt test has finished >*/
  .NumOfData = -1,            /* By default it's '-1'. If you want the engine stops after get NumofData, then set the value here. Otherwise, set it to '-1' which means never stop. */

  /* Describe Ramp signal */
  .RampStartVolt = -400.0f,        /**< The start voltage of ramp signal in mV */
  .RampPeakVolt = 1200.0f,         /**< The maximum or minimum voltage of ramp in mV */
  .Vzero = 400.0f, // vzero = 800 -> vce0 = 195mV at 0x200 vzero = 1100 -> Vce0 = 504mV at 0x200
  .Vbias = 600.0f, // normal 600.0
  .frequency_hz = 10.0f,   /**< The frequency of the ramp signal in Hz */
  .DAC_Steps = 1000,           /**< Total number of steps. Limited to 4095. */
  .ScanRate = 400.0f,              /* Scan rate in V/s */
  /*Configure for HSDAC*/
  .PwrMod = AFEPWR_LP,              /* control chip power mode (LP/HP)*/
  .HstiaRtiaSel = HSTIARTIA_160K,        /* HSTIARTIA_160K*/
  .ExcitBufGain = EXCITBUFGAIN_2,        /* Select from  EXCTBUFGAIN_2, EXCTBUFGAIN_0P25 */    
  .HsDacGain = HSDACGAIN_1,           /* Select from  HSDACGAIN_1, HSDACGAIN_0P2 */
  .HsDacUpdateRate = 10,

  /* Receive path configuration */			
  .ExternalRtiaValue = 0.0f,    /**< The optional external RTIA value in Ohm. Disconnect internal RTIA to use external RTIA. When using internal RTIA, this value is ignored. */
  .AdcPgaGain = ADCPGA_1,           /**< PGA Gain select from ADCPGA_1, ADCPGA_1_5, ADCPGA_2, ADCPGA_4, ADCPGA_9 !!! We must ensure signal is in range of +-1.5V which is limited by ADC input stage */   
  .ADCSinc3Osr = ADCSINC3OSR_2,          /**< We use data from SINC3 filter. */
  .ADCSinc2Osr = ADCSINC2OSR_22,  
  .BpSinc3 = bFALSE, 
  .Sinc2En = bTRUE, 
  .BpNotch = bTRUE,
  .FIFOSrc = FIFOSRC_SINC2NOTCH,

  /* Digital related */
  .FifoThresh = 4,           /**< FIFO Threshold value */

  /* switch configuration*/
  .DswitchSel = SWD_CE0,
  .PswitchSel = SWP_CE0,
  .NswitchSel = SWN_SE0LOAD,
  .TswitchSel = SWT_SE0LOAD| SWT_TRTIA,
};


static void fscv_platform_config(void){
    AD5940_HWReset();
    AD5940_Initialize();

    /* configure clock */
    CLKCfg_Type clk_cfg = {
        .ADCClkDiv = ADCCLKDIV_1,
        .ADCCLkSrc = ADCCLKSRC_XTAL,
        .SysClkDiv = SYSCLKDIV_1,
        .SysClkSrc = SYSCLKSRC_XTAL,
        .HfOSC32MHzMode = bFALSE,
        .HFOSCEn = 0,
        .HFXTALEn = 1,
        .LFOSCEn = bTRUE,
    };
    AD5940_CLKCfg(&clk_cfg);

    /* configure power mode and bandwidth */
    AD5940_AFEPwrBW(AFEPWR_LP, AFEBW_250KHZ);

    /* intial fifo configuration */
    FIFOCfg_Type fifo_cfg = {
        .FIFOEn = bFALSE,
        .FIFOMode = FIFOMODE_FIFO,
        .FIFOSize = FIFOSIZE_2KB,
        .FIFOSrc = FIFOSRC_SINC3,
        .FIFOThresh = 4,
    };
    AD5940_FIFOCfg(&fifo_cfg);

    /* intial sequencer configuration */
    SEQCfg_Type seq_cfg = {
        .SeqMemSize = SEQMEMSIZE_4KB,
        .SeqCntCRCClr = bTRUE,
        .SeqEnable = bFALSE,
        .SeqWrTimer = 0,
    };
    AD5940_SEQCfg(&seq_cfg);

    /* configure interrupt controller */
    uint32_t intc0_src = AFEINTSRC_ENDSEQ | AFEINTSRC_CUSTOMINT0 | AFEINTSRC_DATAFIFOTHRESH | AFEINTSRC_DATAFIFOOF;
    uint32_t intc1_src = AFEINTSRC_ALLINT;
    AD5940_INTCCfg(AFEINTC_0, intc0_src, bTRUE);
    AD5940_INTCClrFlag(AFEINTSRC_ALLINT);
    AD5940_INTCCfg(AFEINTC_1, intc1_src, bTRUE);
    AD5940_INTCClrFlag(AFEINTSRC_ALLINT);

    /* configure GPIO */
    AGPIOCfg_Type gpio_cfg = {
        .FuncSet = GP0_INT | GP1_SLEEP | GP2_SYNC,
        .InputEnSet = 0,
        .OutputEnSet = AGPIO_Pin0 | AGPIO_Pin1 | AGPIO_Pin2,
        .OutVal = 0,
        .PullEnSet = 0,
    };
    AD5940_AGPIOCfg(&gpio_cfg);

    LFOSCMeasure_Type LfoscMeasure = {
        .CalDuration = 1000.0,
        .CalSeqAddr = 0,
        .SystemClkFreq = 16000000.0f,
    };
    AD5940_LFOSCMeasure(&LfoscMeasure, &AppRampCtrl.LFOSCClkFreq);
    ESP_LOGI(TAG, "LFOSC Clock Frequency measured: %.2f Hz", AppRampCtrl.LFOSCClkFreq);
}


static void calculate_hsdac_code(float Vzero, float target_mv, uint32_t *wg_code){
    const float V_POINTS[] = {-472.0f, -42.0f, 426.0f, 910.0f, 1368.0f, 1820.0f, 2275.0f};
    const uint32_t C_POINTS[] = {0x200, 0x400, 0x600, 0x800, 0xA00, 0xC00, 0xE00};
    const int NUM_POINTS = 7;

    // target_mv is already the desired differential voltage
    uint32_t code;

    // Handle out-of-bounds (clamping)
    if (target_mv <= V_POINTS[0]) {
        code = C_POINTS[0];
    }
    else if (target_mv >= V_POINTS[NUM_POINTS - 1]) {
        code = C_POINTS[NUM_POINTS - 1];
    }
    else {
        code = C_POINTS[0];
        for (int i = 0; i < NUM_POINTS - 1; i++) {
            if (target_mv < V_POINTS[i + 1]) {
                float fraction = (target_mv - V_POINTS[i]) / (V_POINTS[i + 1] - V_POINTS[i]);
                code = (uint32_t)(fraction * (C_POINTS[i + 1] - C_POINTS[i]) + C_POINTS[i]);
                break;
            }
        }
    }

    // Final hardware safety clamp
    if (code > 0xE00) code = 0xE00;
    if (code < 0x200) code = 0x200;

    *wg_code = code;
}

static void generate_next_fscv_code(uint32_t * wg_code, uint32_t step_idx, uint32_t fscv_peak_idx, float step_size_mv){
    float target_mv; 
    if (step_idx <= fscv_peak_idx) {
        target_mv = AppRampCtrl.RampStartVolt + step_size_mv * (float)step_idx;
    }
    else {
        uint32_t descending_step_idx = step_idx - fscv_peak_idx;
        target_mv = AppRampCtrl.RampPeakVolt -  step_size_mv * (float)descending_step_idx;
    }
    if (target_mv > AppRampCtrl.RampPeakVolt) {
        target_mv = AppRampCtrl.RampPeakVolt;
    }
    if (target_mv < AppRampCtrl.RampStartVolt) {
        target_mv = AppRampCtrl.RampStartVolt;
    }
    calculate_hsdac_code(AppRampCtrl.Vzero, target_mv, wg_code);
}

static AD5940Err fscv_ramp_seq_gen(void){
    uint32_t fscv_peak_idx = AppRampCtrl.DAC_Steps / 2;
    float step_size_mv = (AppRampCtrl.RampPeakVolt - AppRampCtrl.RampStartVolt) / (float)fscv_peak_idx;
    uint32_t wg_code;

    AD5940_SEQGenCtrl(bTRUE);
    AD5940_SEQGenInsert(SEQ_WAIT((uint32_t)(16e6 * 10e-3))); // Wait 10ms for settling
    AD5940_AFECtrlS(AFECTRL_ADCCNV, bTRUE);
    for (uint32_t step_idx = 0; step_idx < AppRampCtrl.DAC_Steps; step_idx++) {
        generate_next_fscv_code(&wg_code, step_idx, fscv_peak_idx, step_size_mv);
        AD5940_WGDACCodeS(wg_code);
    }

    AD5940_AFECtrlS(AFECTRL_ADCCNV, bFALSE);
    AD5940_SEQGenInsert(SEQ_INT0());
    AD5940_SEQGenCtrl(bFALSE);

    const uint32_t *pSeqCmd; 
    uint32_t SeqLen; 
    AD5940Err error = AD5940_SEQGenFetchSeq(&pSeqCmd, &SeqLen);

    SEQInfo_Type FSCVRampInfo;
    uint32_t SeqStartAddr = 0;
    uint32_t InitSeqId = SEQID_0;
    if (error == AD5940ERR_OK) {
        FSCVRampInfo.SeqId = InitSeqId;
        FSCVRampInfo.SeqRamAddr = SeqStartAddr;
        FSCVRampInfo.SeqLen = SeqLen;
        FSCVRampInfo.pSeqCmd = pSeqCmd;
        FSCVRampInfo.WriteSRAM = bFALSE; 
        AD5940_SEQCmdWrite(FSCVRampInfo.SeqRamAddr, FSCVRampInfo.pSeqCmd, FSCVRampInfo.SeqLen);
    }
    else{
        ESP_LOGE(TAG, "Failed to fetch FSCV ramp sequence, error code: %d", error);
        ESP_LOGE(TAG, "sequence length: %d", SeqLen);
        return AD5940ERR_ERROR;
    }

    float ramp_duration_ms = (AppRampCtrl.RampPeakVolt - AppRampCtrl.RampStartVolt) / AppRampCtrl.ScanRate * 2.0f;

    uint32_t seq_write_timer = (uint32_t)(16e6 * (ramp_duration_ms / 1000.0f) / AppRampCtrl.DAC_Steps);

    FIFOCfg_Type fifo_cfg;
    fifo_cfg.FIFOEn = bTRUE;
    fifo_cfg.FIFOSrc = AppRampCtrl.FIFOSrc;
    fifo_cfg.FIFOThresh = 511;
    fifo_cfg.FIFOMode = FIFOMODE_FIFO;
    fifo_cfg.FIFOSize = FIFOSIZE_2KB;
    AD5940_FIFOCfg(&fifo_cfg);

    SEQCfg_Type seq_cfg;
    seq_cfg.SeqMemSize = SEQMEMSIZE_4KB;
    seq_cfg.SeqBreakEn = bFALSE;
    seq_cfg.SeqIgnoreEn = bFALSE;
    seq_cfg.SeqCntCRCClr = bTRUE;
    seq_cfg.SeqEnable = bFALSE;
    seq_cfg.SeqWrTimer = (uint8_t)seq_write_timer;
    AD5940_SEQCfg(&seq_cfg);

    AD5940_SEQInfoCfg(&FSCVRampInfo);

    AD5940_SEQCtrlS(bTRUE);
    AD5940_INTCClrFlag(AFEINTSRC_ALLINT);
    AD5940_ClrMCUIntFlag();

    return AD5940ERR_OK;

}

static AD5940Err fscv_init_seq_gen(void){
    AD5940_SEQGenCtrl(bTRUE);
    AD5940_AFECtrlS(AFECTRL_ALL, bFALSE);

    AFERefCfg_Type aferef_cfg;
    AD5940_StructInit(&aferef_cfg, sizeof(aferef_cfg));
    aferef_cfg.HpBandgapEn = bTRUE;
    aferef_cfg.Hp1V8BuffEn = bTRUE;
    aferef_cfg.LpBandgapEn = bTRUE;
    aferef_cfg.LpRefBufEn = bTRUE;
    aferef_cfg.Hp1V1BuffEn = bTRUE; // not sure if needed
    AD5940_REFCfgS(&aferef_cfg);

    LPLoopCfg_Type lploop_cfg;
    AD5940_StructInit(&lploop_cfg, sizeof(lploop_cfg));


    uint8_t BITCODE6 = (uint8_t)((AppRampCtrl.Vzero - 200.0f) /34.375f); // LSB 6bit = 34.375mV
    uint16_t BITCODE12 = (uint16_t)(AppRampCtrl.Vbias * 1000.0f / 537.2f) + BITCODE6 * 64; // this is to ensure Vbias is always higher than Vzero, which means we always have positive bias for vCe0, current Vbias = 600 -> vminceo~0, vbias = 1200 -> Vminceo =613mV

    if(BITCODE12 < (BITCODE6 * 64)){
        BITCODE12 = BITCODE12 - 1;
    }

    lploop_cfg.LpDacCfg.LpdacSel = LPDAC0;
    lploop_cfg.LpDacCfg.DacData12Bit = BITCODE12;
    lploop_cfg.LpDacCfg.DacData6Bit = BITCODE6;
    lploop_cfg.LpDacCfg.DataRst = bFALSE;
    lploop_cfg.LpDacCfg.LpDacSW = LPDACSW_VZERO2HSTIA | LPDACSW_VZERO2PIN | LPDACSW_VBIAS2PIN;; // | LPDACSW_VBIAS2PIN
    lploop_cfg.LpDacCfg.LpDacRef = LPDACREF_2P5;
    lploop_cfg.LpDacCfg.LpDacSrc = LPDACSRC_MMR;
    lploop_cfg.LpDacCfg.LpDacVbiasMux = LPDACVBIAS_12BIT;
    lploop_cfg.LpDacCfg.LpDacVzeroMux = LPDACVZERO_6BIT;
    lploop_cfg.LpDacCfg.PowerEn = bTRUE;

    lploop_cfg.LpAmpCfg.LpPaPwrEn = bFALSE;      // disable LP PA - stops it driving CE0
    lploop_cfg.LpAmpCfg.LpTiaPwrEn = bFALSE; 

    AD5940_LPLoopCfgS(&lploop_cfg);

    HSLoopCfg_Type hsloop_cfg;
    AD5940_StructInit(&hsloop_cfg, sizeof(hsloop_cfg));
    /* high speed loop amp config*/
    hsloop_cfg.HsDacCfg.ExcitBufGain = EXCITBUFGAIN_2;
    hsloop_cfg.HsDacCfg.HsDacGain = HSDACGAIN_1; //HSDACGAIN_1 
    hsloop_cfg.HsDacCfg.HsDacUpdateRate = 10;
    /*HSDAC output to CE0*/
    hsloop_cfg.SWMatCfg.Dswitch = SWD_CE0;
    hsloop_cfg.SWMatCfg.Pswitch = SWP_CE0;
    hsloop_cfg.SWMatCfg.Nswitch = SWN_SE0LOAD;
    hsloop_cfg.SWMatCfg.Tswitch = SWT_SE0LOAD | SWT_TRTIA;

    /* HSTIA config*/
    hsloop_cfg.HsTiaCfg.DiodeClose = bTRUE;
    hsloop_cfg.HsTiaCfg.HstiaCtia = 32;
    hsloop_cfg.HsTiaCfg.HstiaRtiaSel = AppRampCtrl.HstiaRtiaSel;
    hsloop_cfg.HsTiaCfg.HstiaBias = HSTIABIAS_VZERO0;
    hsloop_cfg.HsTiaCfg.HstiaDeRload = HSTIADERLOAD_OPEN;
    hsloop_cfg.HsTiaCfg.HstiaDeRtia = HSTIADERTIA_OPEN;
    /* High speed loop waveform generator configuration */
    hsloop_cfg.WgCfg.WgType = WGTYPE_MMR;
    hsloop_cfg.WgCfg.GainCalEn = bFALSE;
    hsloop_cfg.WgCfg.OffsetCalEn = bFALSE;
    AD5940_HSLoopCfgS(&hsloop_cfg);

    uint32_t hsdac_code;
    calculate_hsdac_code(AppRampCtrl.Vzero, AppRampCtrl.RampStartVolt, &hsdac_code);
    AD5940_WGDACCodeS(hsdac_code);

    /* Config DSP */
    DSPCfg_Type dsp_cfg;
    AD5940_StructInit(&dsp_cfg, sizeof(dsp_cfg));
    dsp_cfg.ADCBaseCfg.ADCMuxP = ADCMUXP_HSTIA_P;
    dsp_cfg.ADCBaseCfg.ADCMuxN = ADCMUXN_HSTIA_N;
    dsp_cfg.ADCBaseCfg.ADCPga = AppRampCtrl.AdcPgaGain;
    /*ADC Filter Configuration*/
    dsp_cfg.ADCFilterCfg.ADCSinc2Osr = AppRampCtrl.ADCSinc2Osr;
    dsp_cfg.ADCFilterCfg.ADCSinc3Osr = AppRampCtrl.ADCSinc3Osr;
    dsp_cfg.ADCFilterCfg.BpSinc3 = AppRampCtrl.BpSinc3;
    dsp_cfg.ADCFilterCfg.BpNotch = bTRUE;
    dsp_cfg.ADCFilterCfg.Sinc2NotchEnable = AppRampCtrl.Sinc2En;
    dsp_cfg.ADCFilterCfg.ADCRate = ADCRATE_800KHZ;
    AD5940_DSPCfgS(&dsp_cfg);

    /* Power up necessary blocks: DAC reference buffer, DAC, TIA, waveform generator */
    AD5940_AFECtrlS(AFECTRL_DACREFPWR, bTRUE); //AFECTRL_DCBUFPWR |
    AD5940_AFECtrlS(AFECTRL_EXTBUFPWR | AFECTRL_INAMPPWR | AFECTRL_HSTIAPWR | AFECTRL_HSDACPWR, bTRUE);
    AD5940_AFECtrlS(AFECTRL_WG | AFECTRL_ADCPWR, bTRUE);

    AD5940_SEQGenInsert(SEQ_STOP());
    AD5940_SEQGenCtrl(bFALSE);

    const uint32_t *pSeqCmd;
    uint32_t SeqLen;
    AD5940Err error = AD5940_SEQGenFetchSeq(&pSeqCmd, &SeqLen);

    SEQInfo_Type InitSeqInfo;
    uint32_t MaxSeqLen = 1024; // = 4kb/4
    uint32_t SeqStartAddr = 0;
    uint32_t InintSeqId = SEQID_0;
    if (error == AD5940ERR_OK) {
        AD5940_StructInit(&InitSeqInfo, sizeof(InitSeqInfo));
        if (SeqLen >= MaxSeqLen) {
            ESP_LOGE(TAG, "Generated sequence length %d exceeds max length %d", SeqLen, MaxSeqLen);
            return AD5940ERR_ERROR;
        }

        InitSeqInfo.SeqId = InintSeqId;
        InitSeqInfo.SeqRamAddr = SeqStartAddr;
        InitSeqInfo.pSeqCmd = pSeqCmd;
        InitSeqInfo.SeqLen = SeqLen;
        InitSeqInfo.WriteSRAM = bTRUE;
        AD5940_SEQInfoCfg(&InitSeqInfo);
    }
    else {
        ESP_LOGE(TAG, "Failed to fetch generated sequence: %d", error);
        return AD5940ERR_ERROR;
    }

    AD5940_INTCClrFlag(AFEINTSRC_ALLINT);
    AD5940_SEQCtrlS(bTRUE);
    AD5940_SEQMmrTrig(InitSeqInfo.SeqId);
    while (AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_ENDSEQ) == bFALSE)
        ;
    AD5940_INTCClrFlag(AFEINTSRC_ENDSEQ);
    ESP_LOGI(TAG, "Sequence generator initialized and ran successfully");

    if (fscv_ramp_seq_gen() != AD5940ERR_OK) {
        ESP_LOGE(TAG, "Failed to generate FSCV ramp sequence");
        return AD5940ERR_ERROR;
    }

    return AD5940ERR_OK;
}

static void start_fscv(void) {
    WUPTCfg_Type wupt_cfg;
    wupt_cfg.WuptEn = bTRUE;
    wupt_cfg.WuptEndSeq = WUPTENDSEQ_A;
    wupt_cfg.WuptOrder[0] = SEQID_0;
    wupt_cfg.SeqxSleepTime[SEQID_0] = 4;
    wupt_cfg.SeqxWakeupTime[SEQID_0] = (uint32_t)(AppRampCtrl.LFOSCClkFreq / AppRampCtrl.frequency_hz) - 4;
    AD5940_WUPTCfg(&wupt_cfg);
}

static const float RtiaValue[] = {200.0, 1000.0, 5000.0, 10000.0, 20000.0, 40000.0, 80000.0, 160000.0, 1000000.0};

static void fscv_data_process(uint32_t *app_data_buff, uint32_t *pbuf_len){
    static float s_fscv_samples[APPBUFF_SIZE];

    if (!pbuf_len || *pbuf_len == 0) {
        return;
    }

    if (*pbuf_len > APPBUFF_SIZE) {
        ESP_LOGW(TAG, "FSCV data too large; dropping");
        return;
    }

    size_t bytes = (size_t)(*pbuf_len) * sizeof(float);
    if (bytes > UINT16_MAX) {
        ESP_LOGW(TAG, "FSCV data too large; dropping");
        return;
    }
    for (uint32_t i = 0; i < *pbuf_len; i++) {
        float mv = -AD5940_ADCCode2Volt(app_data_buff[i] & 0xFFFF, AppRampCtrl.AdcPgaGain, AppRampCtrl.ADCRefVolt);
        float current_nA = (mv * 1.0e-3f) / RtiaValue[AppRampCtrl.HstiaRtiaSel] * 1.0e9;

        s_fscv_samples[i] = current_nA;
        printf("Current (nA): %.2f\n", current_nA);
    }

}

static void fscv_ISR(void *pBuff, uint32_t *pCount){
    uint32_t IntFlag = AD5940_INTCGetFlag(AFEINTC_0);
    uint32_t FifoCnt;
    if (IntFlag & AFEINTSRC_CUSTOMINT0){
        FifoCnt = AD5940_FIFOGetCnt();
        if (FifoCnt > 0) {
            AD5940_FIFORd((uint32_t *)pBuff, FifoCnt);
            fscv_data_process((uint32_t *)pBuff, &FifoCnt);
        }
        AD5940_INTCClrFlag(AFEINTSRC_CUSTOMINT0);
    }
    if (IntFlag & AFEINTSRC_DATAFIFOOF) {
        ESP_LOGE(TAG, "FIFO OVERFLOW - data lost");
        AD5940_INTCClrFlag(AFEINTSRC_DATAFIFOOF);
    }
    return;
}

I notice that when set the Vzero = 1100mV, the output of CE0 is 505mV at the DAC code 0x200, which mean after opamp is 1100mV, which I cannot generate wanted ramp (the difference between V_CE0_buffer and VSE0 is about 13mV).

When I set the Vzero = 700mV, the difference between V_CE0_buffer and VSE0 is about -472mV at the DAC code 0x200.

If I set Vzero to be less than 700mV (Vzero = 500mV), the difference between V_CE0_buffer and VSE0 is about -463mV at the DAC code 0x200, the same with when the Vzero is 700mV.

The detailed of my measurement is below:

        // this is before buffer voltage; vbias = 200mV, vzero = 1100:                  0x200: 505mV;  0x400: 705mV;   0x600: 905mV;  0x800: 1110mV ; 0xA00: 1310mV; 0xC00: 1517mV ; 0xE00: 1719mV
        // with 15kohm load, vzero = 1800, vbias = 600; voltage after buffer - vzero:   0x200: 814mV;  0x400: ;        0x600: ;       0x800: ;        0xA00: ;       0xC00: ;        0xE00: 3.03V;
        // with 15kohm load, vzero = 1100, vbias = 600; voltage after buffer - vzero:   0x200: -13mV;  0x400: 425mV;   0x600: 866mV;  0x800: 1310mV;  0xA00: 1.75V ; 0xC00: 2.19V;   0xE00: 2.63V;
        // with 15kohm load, vzero = 700, vbias = 600; voltage after buffer - vzero:    0x200: -472mV; 0x400: -42mV ;  0x600: 426mV;  0x800: 910mV;   0xA00: 1.368V; 0xC00: 1.820V;  0xE00: 2275mV;
        // with 15kohm load, vzero = 700, vbias = 200; voltage after buffer - vzero:    0x200: -474mv; 0x400:  ;       0x600: ;       0x800: 909mV;   0xA00: ;       0xC00: 1.820V ; 0xE00: 2.270v ; -> Vbias currently not affecting the output
        // with 15kohm load, vzero = 500, vbias = 600; voltage after buffer - vzero:    0x200: -463mV; 0x400:  -230mV; 0x600: 400mV;  0x800: 910mV;   0xA00: 1.367V; 0xC00: 1.819V;  0xE00: 2.269V;

Moreover, when I set different Vbias, the DC bias of the ramp does not change.

I don't understand this dependency on Vzero when Vzero > 700mV and why when I change Vbias, nothing change.

Is my setup incorrect? Can you give me lead into how to solve this?

Thank you very much.

Sincerely,

Lizzie

Can you please help

ADC sends out the same value every time

vbash — Sun, 05 Apr 2026 11:20:22 GMT

Hello,

I am trying to debug a new ADC board based on LTC2325-16. I have developed some HDL to generate CNV and clock pulse and read the SDO lines in DDR mode. As you can see from the image, the digital interface appears to working correctly:

My problem is regardless of what signal I apply to analog input pins of ADC the output on SDO lines remains the same values, dancing around -64 and all even numbers.

Here is part of the schematic. I also have an analog front-end using an FDA but I think it is not relevant at the moment because I am applying an analog signal directly to ADCs Ain+- pins.

I would appreciate it if anyone could give me an idea of what is happening.

For the information, the CNV and SCK are coming directly from the FPGA (with no jitter filter between them) and the frequency of the clock is 50 Mhz. I have a 10ns delay between the falling edge of the CNV and the first rising edge of the clock. Also since CLKOUT and SDOx are in phase, I pass the SDOx through a 5ns delay in order to capture them at falling and raising edges of CLKOUT

Using ADAS1000 with SDP USB Converter

bdogan — Thu, 02 Apr 2026 12:25:10 GMT

Dear Analog Devices Support Team,

I am currently using the ADAS1000 board together with the SDP USB converter in my ECG PhD project, and I would like to ask a few technical questions.

Using ADAS1000 directly from MATLAB or Python
Is it possible to communicate with and use the ADAS1000 directly from MATLAB or Python instead of only through the ADAS1000 GUI? I need to analyze the ECG signals online/in real time during my experiments.
Could you please share any available libraries, APIs, SDKs, example code, or other required software/documentation for this purpose?
ADAS1000 GUI compatibility with newer Windows versions
The ADAS1000 GUI seems to work only on older Windows 7 computers in my case. Is there a newer or updated version of the software that supports current Windows versions?

I would appreciate any guidance, software resources, or documentation you can provide.

Current consumption of the AD7608

miky — Thu, 02 Apr 2026 08:35:21 GMT

Hello.

I have a question about AD7608.

The specifications in the datasheet list “Itotal.”
Does this refer to the total current for both the digital and analog power supplies?

I would like to verify the current consumption for the digital and analog sections separately.
If you have any documentation or calculation methods available, please provide them.

Best regards.

Weird data on MISO line, after reading out all 8 channels of the on ad7771 ADC

Ol40 — Wed, 01 Apr 2026 16:31:34 GMT

Hello everyone, i'm currently working with the ad777x-FMCZ devkit, and reading out the channels works fine.
what i'm having trouble with is noticing some weird behaviour on the MISO line, after finishing readiout out all 8 channels.

this is with reading the channels only through SPI. happens when i read the channels in 8 byte frames, or when i try to read all 32 bytes at once.

I might be doing something wrong because for the life of me I cannot understand what is meant in this section of the data sheet.

tbh i think it's quite weirdly written

but in any case, here's what happens on the signal analyzer, first in 8 byte chunk readout.

lines are top to bottom: clock, mosi, miso, /cs,drdy,alert

as you can see, after the last 8 byte chunk is read out, after a while, and after the chip select line is pulled high, we have some weird bit of noise on the line

here is the same thing happening when i try to read out all 32 bytes at once.

i'm sending 0x80 command every 4 bytes, so looks like 0x80, 0x00, 0x00, 0x00, 0x80..... so as to not trigger a reset.

any idea why this might be happening?, the data that i'm getting seems to be good otherwise.

ADAS1000-4: Minimal reference schematic for basic ECG acquisition and QRS visualization

AE61 — Wed, 01 Apr 2026 12:48:53 GMT

Hello,

I am currently developing a small ECG device as part of my final thesis and I selected the ADAS1000-4 because it seems to be a very capable solution for compact ECG acquisition.

At the moment, I am not trying to build a full advanced medical system yet. My immediate goal is much simpler: I want to establish a minimal and technically correct hardware baseline that allows me to acquire ECG signals and visualize a clear QRS complex.

I have already started my own schematic draft based on the datasheet, including the basic ECG input path, protection concept, clocking, and power supply considerations. However, before I continue too far, I would like to ask whether Analog Devices can provide or point me to any of the following specifically for the ADAS1000-4:

a minimal reference schematic for basic ECG acquisition
an evaluation board schematic
an application note with a proven front-end example
or any recommended minimal hardware configuration for simply acquiring ECG data and displaying a visible QRS complex

At this stage, I do not need a complete production-ready system. A known-good minimal reference design for basic ECG signal acquisition would already be extremely valuable and would help me build a solid foundation for my thesis project.

If helpful, I can also share my current schematic draft for context.

Thank you very much for any guidance.

Best regards,
Atakan

Keil build error

Lilij — Tue, 31 Mar 2026 03:39:38 GMT

I am trying to build the AD5940_SPI example for ADICUP3029 using Keil uVision 5 with ARM Compiler 6.24.

The project compiles successfully, but linking fails with:

Error: L6320W: Ignoring --entry command. Cannot find argument 'Reset_Handler'
Warning: L6320W: Ignoring --first command. Cannot find argument '__Vectors'

Result: target not created (.axf not generated)

What I have verified:
- Using ADICUP3029 target
- Correct startup file: startup_ADuCM3029.s
- system_ADuCM3029.c present (no duplicates)
- __Vectors and Reset_Handler are defined and exported in startup file
- Clean + rebuild performed
- OUT folder deleted and regenerated

Observations:
- Using ARM Compiler 6 (armclang), not legacy ARMCC
- No scatter file manually set (default memory layout used)
- Project compiles all CMSIS/DSP files without issue
- Linker cannot resolve startup symbols

Question:
Is this example compatible with ARM Compiler 6, or does it require ARM Compiler 5?

If AC6 is supported, what is the correct startup/linker configuration required for ADICUP3029?

If not, what is the recommended working toolchain setup for this example?

Thanks.

Request for EVAL-AD4130-8 PCB design files

mcvain — Tue, 31 Mar 2026 01:49:50 GMT

Can the PCB design file and schematic for the eval board please be shared with me (mcvain77@gmail.com)? I see others have received it via email through this forum.

AD5941 Schematic Design

damocrrll — Mon, 30 Mar 2026 08:44:14 GMT

Dear team,

I bought the chip of AD941, and then designed the PCB diagram by myself for testing electrochemical methods , can you help me see if there is a problem with my schematic?

kind regard!

Exact 'Wideband Filter' Step Response numbers

Tobalt — Mon, 30 Mar 2026 08:27:55 GMT

We are using the AD7768-4 for a high precision measurement instrument. Recently, transient measurements have become an application, and the wideband decimation filter expectably leads to step response oscillations, as also given by Figure 92 of the data sheet.

In order the deconvolve this behavior, we need to know the ideal step response. Could you please provide the numeric step response coefficients?

Best regards!

About the ADA4084, the REF buffer on the ADAQ4224 evaluation board.

yoshibabababa735 — Fri, 27 Mar 2026 08:46:06 GMT

In the ADAQ4224evaluation board(EVAL-ADAQ4224-FMCZ), the ADA4807 is operated with a 5V supply in a voltage follower configuration for a 4.096V output.

Since VICM is operating outside the recommended range $V_S - 1.5V$ , the DC precision is expected to deteriorate. Is this considered a valid operating condition for this evaluation board?

16-bit mode data format issue

HJM — Fri, 27 Mar 2026 07:20:16 GMT

In the evaluation software of AD4115, we used the 16-bit mode of AD4115 to read the data from the data_register register of the ADC conversion. We captured the waveform at that time. According to the description in the datasheet, it should be an 8-sck command followed by 16-sck data. However, when we captured it, we found that it was 16-sck + 16-sck (as shown in the following figure). This does not match the description in the datasheet. In our application, which configuration should we follow (datasheet or evaluation software)?

Thanks

What power mode can we used?

Firefighter — Fri, 27 Mar 2026 05:39:31 GMT

Hi ADI,

In the table 9 of datasheet for ad7768-1, it suggests the fmod can only go up to 1.024MHz.

However, in the online tool https://www.analog.com/media/en/engineering-tools/design-tools/ad7768-1_filter_model_web.xlsx, we can use 4MHz with low power mode. We want to set divider to 1 and demation to 1024 with 4MHz fmod coz it give us a very low noise value.

We want to know whether the configuration is supported or not.

Thanks!

Purchase of an EVAL-AD4857 populated with an AD4853

charlesw — Wed, 25 Mar 2026 16:38:45 GMT

I would like to purchase an EVAL-AD4857 evaluation board that is populated with the 4-channel version, AD4853. Essentially an EVAL-AD4853. Is this possible?

AD74416 EVA Board measurement Popcorn noise occurred

Osamukan — Tue, 24 Mar 2026 06:37:26 GMT

Hello.

When using a dummy load to verify the characteristics of the EVAL-AD74416H evaluation board, a popcorn-like noise was obtained.

It did not appear with only one channel, but was visible on all channels when the dummy load was included.

Furthermore, it was not synchronized with the SYNC function as shown in Fig. 4 and Fig. 8 in the datasheet.

The source of this noise is unknown.

Best regards

Noisy ECG signal using EVAL-AD5940BIOZ and AD8233 (3-Wire Setup)

Sadique — Tue, 24 Mar 2026 00:48:49 GMT

Hello everyone,

I am currently evaluating the AD5940 and AD8233 for ECG acquisition, but I am struggling with an extremely noisy signal where the P-QRS-T waveform is buried/indistinguishable.

My Hardware Setup:

Motherboard: EVAL-ADICUP3029

Middle Shield: EVAL-AD5940ARDZ

Top Shield: EVAL-AD5940BIOZ (Integrated AD5940-BioElectric board)

Software: Testing baseline hardware functionality using the SensorPal GUI.

My Connections & Configuration: I am using a 3-lead ECG snap cable plugged into the P6 micro-USB port on the top BioElectric shield, using wet Ag/AgCl gel pads attached to a human subject.

Red (F+): Left Arm

Blue (S-): Right Arm

Black (F- / RLD): Right Leg

After initially dealing with amplifier saturation/flatlining, I referenced the board schematics and corrected my jumpers to the following configuration to properly balance the DC Lead-Off detection and reference bias:

P16: Pins 1-2 (Pulled up to ELECT_BIAS)

P17: Pins 2-3 (Pulled down to AGND)

JP7: Pins 1-3 (REFOUTS connected to ELECT_BIAS)

P18 / P19: DNI (Empty)

The Issue: While correcting the jumpers successfully resolved the flatline, the resulting signal in SensorPal is extremely noisy.

My Questions:

1. Are there any other specific hardware jumpers or surface-mount components (like JP4, JP5, JP6) that I need to modify from their factory defaults to clean up this noise for a 3-wire setup?

2. Since the official custom cable includes a 4th wire (S+ / Green) that I am not using, does the AD8233 on this specific evaluation board require that 4th connection for proper noise cancellation?

3. Are there any specific settings within SensorPal (or the underlying C-code libraries) I should tweak to improve the filtering?

Any guidance on how to achieve a clean baseline ECG with this board would be greatly appreciated! Thank you.

Inverse output when change setting configurations

skindepth — Mon, 23 Mar 2026 01:18:29 GMT

Hi, I am junhyeob from korea.

I have a question with AD7746 difference measuring way.

#	VDD	Cap Vol. (x n)	Conversion time (ms)
Ref	3.3	1/8	11
A	3.3	1/8	77
B	3.3	1/2	11
C	3.3	1/2	77

I had changed settings of ad7746, the test output is different.

In high humidity situation (80%), ref output is different compared to A, B, C test conditions.

In ref test condition, the output in the 80%RH was higher than 60%RH.

But In the A, B, C conditions, the output in the 80%RH was lower than 60% RH.

Is it possible?

or Any ohter suspicious things in my test?

Thank you for reading.