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Register configuration for ADAS1000-4 and ADAS1000-2 12 Leads configuration

I am working with these 2 ICs, and I have already configured registers for get working in 12 leads configuration measurement. You can see this in the previous post. However the signal recollected in the second chip is not the expected.

As you can see, signals coming from ADAS1000-4 (L1, L2, L3, AVR, AVL, AVF and V2) are correct, but signals coming from ADAS1000-2 (V3, V4, V5, V6 with exception of V1) are wrong. 

In ADAS1000-2 I have configured this registers:

reg = ADAS1000.REG_CMREFCTL
val = ADAS1000.MASK_CMREFCTL_LARLD | \
      ADAS1000.MASK_CMREFCTL_LLRLD | \
      ADAS1000.MASK_CMREFCTL_RARLD | \
      ADAS1000.MASK_CMREFCTL_V1RLD | \
      ADAS1000.MASK_CMREFCTL_V2RLD | \
      ADAS1000.MASK_CMREFCTL_CEREFEN | \
      ADAS1000.MASK_CMREFCTL_EXTCM

reg = ADAS1000.REG_FRMCTL
val = ADAS1000.MASK_FRMCTL_RESPPHDIS | \
      ADAS1000.MASK_FRMCTL_GPIODIS | \
      ADAS1000.MASK_FRMCTL_CRCDIS | \
      ADAS1000.MASK_FRMCTL_DATAFMT | \
      ADAS1000.MASK_FRMCTL_SKIP_4TH

reg = ADAS1000.REG_ECGCTL
val = ADAS1000.MASK_ECGCTL_LAEN | \
      ADAS1000.MASK_ECGCTL_LLEN | \
      ADAS1000.MASK_ECGCTL_RAEN | \
      ADAS1000.MASK_ECGCTL_V1EN |  \
      ADAS1000.MASK_ECGCTL_V2EN | \
      ADAS1000.MASK_ECGCTL_GAIN_2_8 | \
      ADAS1000.MASK_ECGCTL_VREFBUF | \
      ADAS1000.MASK_ECGCTL_CLKEXT | \
      ADAS1000.MASK_ECGCTL_GANG | \
      ADAS1000.MASK_ECGCTL_HP



In ADAS1000-4 I have configured this registers

reg = ADAS1000.REG_CMREFCTL
val = ADAS1000.MASK_CMREFCTL_LARLD | \
      ADAS1000.MASK_CMREFCTL_LLRLD | \
      ADAS1000.MASK_CMREFCTL_RARLD | \
      ADAS1000.MASK_CMREFCTL_CERLD | \
      ADAS1000.MASK_CMREFCTL_CEREFEN | \
      ADAS1000.MASK_CMREFCTL_DRVCM | \
      ADAS1000.MASK_CMREFCTL_RLD_EN | \
      ADAS1000.MASK_CMREFCTL_SHLDEN

reg = ADAS1000.REG_FRMCTL
val = ADAS1000.MASK_FRMCTL_V1DIS | \
      ADAS1000.MASK_FRMCTL_V2DIS | \
      ADAS1000.MASK_FRMCTL_RESPPHDIS | \
      ADAS1000.MASK_FRMCTL_GPIODIS | \
      ADAS1000.MASK_FRMCTL_CRCDIS | \
      ADAS1000.MASK_FRMCTL_DATAFMT | \
      ADAS1000.MASK_FRMCTL_SKIP_4TH

reg = ADAS1000.REG_ECGCTL
val = ADAS1000.MASK_ECGCTL_LAEN | \
      ADAS1000.MASK_ECGCTL_LLEN | \
      ADAS1000.MASK_ECGCTL_RAEN | \
      ADAS1000.MASK_ECGCTL_GAIN_2_8 | \
      ADAS1000.MASK_ECGCTL_VREFBUF | \
      ADAS1000.MASK_ECGCTL_CLKEXT | \
      ADAS1000.MASK_ECGCTL_MASTER | \
      ADAS1000.MASK_ECGCTL_GANG | \
      ADAS1000.MASK_ECGCTL_HP


Can you indicate me if my register configuration is correct or I need to change something for get the desired functionality.

  • Hello Jefferson,

    Thanks for message and detailed information.

    A very quick question to ensure i understand correctly - when you say V3 etc are wrong - what do you mean?

    It looks like they are returning a ~1mV signal similar to the other channels? The offset voltage looks different, but that may be expected.

    best regards,

    Catherine

  • Hi Jefferson,

    Ok, understood, the P wave should be positive.

    How do you bring the RA electrode to the ADAS1000-2? (are you bringing it from the master CM_OUT to the Slave CM_IN

    Can you repeat measurement with following small edit and see if things change?

    In ADAS1000-2

    reg = ADAS1000.REG_CMREFCTL
    val = ADAS1000.MASK_CMREFCTL_LARLD | \
          ADAS1000.MASK_CMREFCTL_LLRLD | \
          ADAS1000.MASK_CMREFCTL_RARLD | \
          ADAS1000.MASK_CMREFCTL_V1RLD | \
          ADAS1000.MASK_CMREFCTL_V2RLD | \
          ADAS1000.MASK_CMREFCTL_CEREFEN

  • The wave P (wave preceding the QRS) which in the derivation from V3 to V6 should be positive while in the track it is rather negative. This means that from V3 to V6 dont have the expected shape. My first observation where the problem is localized is the register configuration of ADAS1000-2 which is in charge to get this signal V3 to V6 and V1.

  • Hi Jefferson,

    Both don't need to be set, I believe that CEREFEN will take priority over EXTCM (that's what i read from looking more in depth into the design).

    The bits control different swtiches internally. I don't know that making this digital change will change the bahaviour of what you are seeing, but at the moment, it's the only thing that I see worth trying. I think it's worth checking when you get back to the device next week.

    If no change observed, then we'll move on from there and see what next.

    In the meantime, could you share your schematic?

    thanks...

    Catherine.

  • I am far away of the device in these days, I will check next week. However, I am reading again the datasheet and there is something that is not clear for me. CEREFEN bit and EXTCM bit are similar in his functionality, both of these enable CM_IN, The only difference is EXTCM has high priority that the other one, while the  CERFEN allow to work with other channel signal as LACM for example. What is the main purpose of this?

  • This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

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    EZ Admin