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LTC2321-16

HOD
on Jul 18, 2018

Hi

I have a question LTC2321-16.

Is it okay if we can change the 220pF in front of the ADC to 10pF?

 

 

Best Regards

HOD

  • 0
    •  Analog Employees 
    on Jul 18, 2018 7:23 PM over 2 years ago

    This capacitor serves as a charge reservoir to absorb the sampling transients from the ADC.  There is generally a balance between the peak value of the transient and the time it takes for the transient to settle out.  You can reduce the value of this capacitor quite a bit before you encounter settling time issues.  Even a 10pF capacitor should settle to within 16 bit accuracy after about 8nsec.

    The reason this capacitor is 200pF is to reduce the noise reaching the ADC input.  It is part of an RC filter, which serves as an anti-aliasing lowpass.  As it stands, the 3dB bandwidth of the filter is near 14.5MHz.  Reducing the capacitor to 10pF will increase this bandwidth to several hundred MHz.  That will reduce the SNR, as well as allow higher frequency signals to alias into the sampled output.

    Let me ask why you would like to reduce this capacitance?

  • 0 on Aug 9, 2018 6:43 AM over 2 years ago

    Hi

    Thank you for your answer.

    We are investigating detailed timing of the SPI between the LTC2321-16 and the ASIC,
    There was an unclear point about the ADC timing characteristic on the data sheet and it was informed.

    Please confirm below and thank you for your answer.

    ① Is there data on SCK standard of t_dclkoutsdov, t_hsdo?
    In this usage method, since CLKOUT can not be used, SCK output from the ASIC side is used.
    In considering the setup / hold of the ASIC side,
    Since t_dclkoutsdov, t_hsdo, etc. are regulated based on CLKOUT, timing calculation can not be performed.

    ② If there is no such data,
    Is there a maximum value of t_dsckclkout?
    Worst case calculation is possible if the maximum delay of CLKOUT is known from SCK.
    Best Regards
    HOD
  • 0
    •  Analog Employees 
    on Aug 11, 2018 12:46 AM over 2 years ago

    Unfortunately we don't have a spec we can guarantee SCK to CLKOUT max delay.  If you are using the SCK signal as it leaves the ASIC, you will also have to account for the transit time from ASIC to ADC.

    The best way is to use the CLKOUT signal to time the data entering the ASIC.

  • 0
    •  Analog Employees 
    on Aug 24, 2018 12:52 PM over 2 years ago
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin