AD7177-2, Missing conversions

Hi,

I'm having a particularly weird issue where I'm not receiving half of the converted values. When streaming conversions, I will receive three (seemingly) consecutive conversions, and then three or four conversions disappear, and then I'll get another three seemingly consecutive conversions. 

I know I'm getting 3 and missing 3 (or 4) because I'm feeding a sine wave in the ADC ch0 input and plotting the converted values on my computer. Every 3 points, there's a jump. 

Does this seem like a familiar issue? Am I somehow not accounting for some cooldown period?

I'm currently operating the chip in:

Ch0 on (Ch1,2,3 are all off)

Continuous Conversion mode (Sync_en off, Err_en = 11)

10KSps

WL32

Default Setup0, Gain0, Offset0

Internal reference

IOCLK = 500Khz

Parents
  • 0
    •  Analog Employees 
    on Jun 3, 2018 7:05 PM over 2 years ago

    Hi,

    Can you clarify the value of your Channel register, Is that supposed to be 0x8004? 0x0804 is not a valid data for a channel register. I would also like to know if you are operating in split supply? If you could also stop reading the conversion and just monitor the DRDY pin, does it pulsing at selected ODR? Usually, when DRDY stops pulsing at any time and it stays high or low, this indicates that the serial interface has become asynchronous that means incorrect number of SCLK pulses or there could be glitches on the SCLK line. Please ensure that the correct number of SCLK pulses are being used for each read/write operation. Can you check on the clock pulses? Do you have a scope shot of your digital interface?

    Thanks,

    Jellenie

Reply
  • 0
    •  Analog Employees 
    on Jun 3, 2018 7:05 PM over 2 years ago

    Hi,

    Can you clarify the value of your Channel register, Is that supposed to be 0x8004? 0x0804 is not a valid data for a channel register. I would also like to know if you are operating in split supply? If you could also stop reading the conversion and just monitor the DRDY pin, does it pulsing at selected ODR? Usually, when DRDY stops pulsing at any time and it stays high or low, this indicates that the serial interface has become asynchronous that means incorrect number of SCLK pulses or there could be glitches on the SCLK line. Please ensure that the correct number of SCLK pulses are being used for each read/write operation. Can you check on the clock pulses? Do you have a scope shot of your digital interface?

    Thanks,

    Jellenie

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