AD7177-2, Missing conversions


I'm having a particularly weird issue where I'm not receiving half of the converted values. When streaming conversions, I will receive three (seemingly) consecutive conversions, and then three or four conversions disappear, and then I'll get another three seemingly consecutive conversions. 

I know I'm getting 3 and missing 3 (or 4) because I'm feeding a sine wave in the ADC ch0 input and plotting the converted values on my computer. Every 3 points, there's a jump. 

Does this seem like a familiar issue? Am I somehow not accounting for some cooldown period?

I'm currently operating the chip in:

Ch0 on (Ch1,2,3 are all off)

Continuous Conversion mode (Sync_en off, Err_en = 11)



Default Setup0, Gain0, Offset0

Internal reference

IOCLK = 500Khz

  • 0
    •  Analog Employees 
    on May 31, 2018 4:30 AM over 2 years ago


    May I know what is your input signal amplitude and frequency? May I know also how many data points you sample on your measurements? If you could share to me your digital interface or the data you measured from a specific input signal, it would be great. According to the nyquist theorem, the sampling rate must be at least twice the highest input frequency component. Please take note also that the part requires a settling time at the very first conversion so it has different Tsettle at the first conversion and then the succeeding conversion will occur at the selected ODR. Same thing can be applied to the number of samples, the minimum number of samples (conversions) needed to replicate the signal is at least twice the ratio of your ODR/input frequency since the part needs the filter settling time at the very first conversion. The AD7177 is intended for dc type application, when you tried to input a pure dc signal, are you experiencing the data jump?



  • Hi Jellenie,

    I'm just testing the part with a 30 Hz, 1V pkp sine wave and I've set the output data rate to 10Ksps.

    Right now I'm only using one channel in continuous conversion mode and I'm framing each read with a CS pulse. Below are the following register values:

    Ch0:            16'h0804

    Setup0:        16'h0f30

    FilterCon0:  16'h0507

    ADCMode:  16'h8000

    GPIOCon:   16'h0600

    IFMode:       16'h0102

    My IO frequency is 625Khz.

    My interface works as such:

    My SPI reads the status register and checks that there is a ready conversion. If there is a ready conversion, it reads the data register. 

    What's really really odd is that I have to read the status register an irregular number of times before a conversion is ready. Sometimes I need to read the status register 4 times, sometimes just once. 

  • 0
    •  Analog Employees 
    on Jun 3, 2018 7:05 PM over 2 years ago


    Can you clarify the value of your Channel register, Is that supposed to be 0x8004? 0x0804 is not a valid data for a channel register. I would also like to know if you are operating in split supply? If you could also stop reading the conversion and just monitor the DRDY pin, does it pulsing at selected ODR? Usually, when DRDY stops pulsing at any time and it stays high or low, this indicates that the serial interface has become asynchronous that means incorrect number of SCLK pulses or there could be glitches on the SCLK line. Please ensure that the correct number of SCLK pulses are being used for each read/write operation. Can you check on the clock pulses? Do you have a scope shot of your digital interface?



  • 0
    •  Analog Employees 
    on Aug 24, 2018 12:51 PM over 2 years ago
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin