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AD7193 Accuracy Issues...

   Hello,

AD7193 calibration issue is solved & now i am getting values of offset register & Full scale register as follows.

      Offset register=8389236

      Full scale register=5584950

  AD7193 Configured as follows:

Mode register=0x0C0060

Configuration register=0x040118

Gain=1, Vref1=2.5, Chop disable, FS[9:0]=96,Continuous conversion mode,unipolar configuration

0 to 2.5V dc input connected to ch1 to check linearity of  ADC.

But i am getting 3.5% error (of the reading) near 0.1V

Zero: 0v , ADC counts=0

Span: 2.5V, ADC counts = 16754713

i/p                   ADC counts          Calculated Counts        Error(%)

0.10001          644500                     670228                     3.8387

0.20001         1315798                   1340390                    1.8346

0.30001         1987091                    2010551                   1.1668

0.4001            2660577                   2681316                   0.7734 

0.5001            3331311                   3351478                   0.6017

0.6001            4002490                   4021639                   0.4761

.......

.......

2.0001            13398607                  13403902                0.0394

2.2001            14741788                  14744225                0.0165

2.4001            16083274                  16084548                0.0079

2.5001            16754713                  16754713                

 

 

Please help me how to minimize Error..

Expected error for my application should be <.25% of the reading near zero.

 

Any help will greatly appreciated...

  • Hi,

    Does your measurement requires faster ODR? If not, can you try to enable chopping? With chopping enabled, the offset equals ±0.5 uV typical. Therefore, chopping gives an improvement in offset for gains of 1 to 64. The offset drift is better when chopping is enabled for gains of 1 to 16. May I know if you are using internal or external reference? How your inputs connected? On your configuration register, does your buffer enable? If yes, the inputs should meet the buffer headroom, otherwise linearity and noise performance degrade. If you could also share us the schematic or setup of your measurements it would be great. Since you are targeting precision measurements, care must be taken on the said setup as longer wires or improper grounding connections may introduce some noise and errors.

    Thanks,

    Jellenie

  • Hi..

    apologies. I was just putting the result which i got during testing of ad7193 not targeting precision measurements.

    i want guidance to achieve accurate result...

    I tried with chopping enable mode but unfortunately results are same.

    Buffer is enabled.

    Ref=External ref 2.5V (ADR381)

    Please find attached schematic for your reference..

    Awaiting for your valuable reply.

    Thanks in advance.

              

  • Hi, Latika.

    May I know where the IP2 connected in the circuit? If the input buffer is enabled, the absolute AIN voltage limit at each input pin must be within AGND+250mV to AVDD-250mV. Can you also monitor the output of your reference? Can you try to perform noise test by shorting your inputs AIN1 to AIN2 and put a bias voltage of 1.25V(midscale) and perform conversion. What value did you get? Can you repeat this at 100 samples and get the rms noise and peak to peak noise? If you could also measure the actual input voltage at AIN1 and AIN2 with multi meter and compare it with the input voltage directly from your source just to check if there is already an offset or noise error from the transmission line itself. Have you also followed the grounding and layout consideration suggested on the datasheet? We also have an evaluation board and you can use this as your reference as this is already tested and working based on the datasheet specifications. 

    Thanks,

    Jellenie

  • Hi,

    Apologies. I thought from the figure AIN1 and AIN2 is your enabled channel. What do you mean by channel 1 enabled? From your configuration register, it seems that you have enabled channel 0 which corresponds to inputs AIN1 and AIN2. So, I would like to know what input voltage is present on your enabled input pins. Can you clarify this please.

    Thanks,

    Jellenie

  • Hello mam,

          Presently only one (channel 1) is enabled & input connected to channel 1& channel one is configured as pseudo differential. (IP2-IP7  or AN2-AN7 ) not in used.

    Reference o/p i am getting from from ADR381=2.4995V.

    Also ADC counts noted in the reading is average of 100 samples.

    I will try with other solutions & get back to you soon.

  • Hello,

    Apologies.

    Channel 0 is enable which is corresponds to AIN1 in pseudo differential mode. 

    Input source 0-2.5V is connected to AIN1 PIN No.11 of AD7193.

  • Hello,

    AIN1 & AIN2 shorted together & 1.25V fixed reference is applied [ref IC 33312].

    if i configure AIN1 to pseudo differential mode ADC counts=8363233 [offset register=8389230]

    if i configure it to differential mode ADC counts=00000048.

  • Hi, Latika.

    If 0 to 2.5V is connected to AIN1 with buffered enable, you need at least 250mV headroom, thus the input is restricted from 0.25 to 2.5V. Same with the AINCOM input pin. In your schematic it seems that you have directly connected the AINCOM to GND (0V), the buffer will be non-linear outside this range so the device will be unable to meet the datasheet specifications.

    Thanks,

    Jellenie

  • Hi,

    Yes, if you connect AINCOM with 1.25V, AIN1 can have an input voltage range of 1.25 to 3.75V with Gain=1,Vref=2.5V, unipolar mode. This will still be equivalent to 0 to 2.5V input voltage range.

    Thanks,

    Jellenie

  • Hi, Latika.

    If your application require a differential inputs, you do not need to use the AINCOM pin as this is intended for pseudo differential input. You can either left this open or connect it to GND assuming that there's no other pseudo differential channel is enabled. Regarding the SYNC pin, when this pin is taken low, the modulator and filter are held in a reset state without affecting any of the setup conditions of the part. When \SYNC is taken high, the ADC begins sampling/starts conversion which allows the user to start gathering samples at a known point in time. It does not need to synchronize with SCLK and it can use with single or continuous conversion mode.

    Thanks,

    Jellenie