Hello,
We're driving an EVAL-AD4195-4 over SPI from our own microcontroller rather than the ACE software. Every internal or system zero-scale calibration sets ADC_CONV_ERR (ERROR register bit 3), yet the offset it produces appears correct. We'd like to understand why, and whether the calibration can be trusted.
Setup
- ID registers: CHIP_TYPE 0x07, PRODUCT_ID 0x004C, CHIP_GRADE 0x04, SPI_REVISION 0x83.
- Supplies: seen with SW1 in position 1 (AVDD 5 V, AVSS GND) and in position 2 (AVDD +2.5 V, AVSS -2.5 V, LK21-LK28 removed).
- Internal oscillator, divide by 2 (CLOCK_CTRL 0x0000). Internal reference enabled (REF_CONTROL 0x0001).
- Every setup: AFE 0x0050 (REFOUT/AVSS, bipolar, gain 1), FILTER 0x0000 (Sinc5 + Avg), FILTER_FS 5000, MISC 0x0000. Each channel uses its own setup (CHANNEL_SETUPn = n).
- Per-channel data registers (ADC_CTRL bit 7 = 0), RDY on DIG_AUX1 (PIN_MUXING 0x0010), SPI CRC enabled, ERROR_EN 0x30BC.
- Channels tested: CH0 = AIN0/AIN1 (LK2 fitted) and CH3 = AIN7/AIN8 shorted with a jumper at J1.
Calibration sequence
1. ADC_CTRL = 0x0007 (idle)
2. CHANNEL_EN = the target channel only
3. Clear ERROR (write 1 to any set bits) and confirm it reads 0x0000
4. ADC_CTRL MODE = 1010 (internal zero-scale) or 1000 (system zero-scale)
5. Wait for RDY to go low (about 20 ms), then read ERROR and the channel's OFFSET register
What we see
- ERROR reads 0x0008 after every calibration we have run (more than 40).
- OFFSET is updated to a plausible, repeatable value (-122 to -126 across CH0 and CH3), consistent with each channel's uncalibrated reading of about -165 codes (-49 uV). Afterward the channel reads 0 +/-1 code.
- GAIN stays at 0x555555. A calibrated and an uncalibrated channel measuring the same internal (AVDD-AVSS)/5 input differ by 50 uV, i.e. by the removed offset only, so the gain path is unaffected.
What we have ruled out
- Normal conversions never set the bit: 1,000 continuous conversions across four channels, and 40 single conversions (MODE 0100) on the same isolated channels, all left ERROR at 0x0000.
- A deliberate over-range ((AVDD-AVSS)/5 at gain 4) does set ADC_CONV_ERR during continuous conversion, as documented.
- Timing: ERROR is still 0x0000 immediately after the calibration is triggered and about 10 ms into it. The bit is set by the time RDY goes low.
- It doesn't depend on: internal vs. system zero-scale; channel (CH0, CH3); FILTER_FS 5000 vs. 4; PGA gain 1 vs. gain 1 with precharge buffer; CHOP_ADC enabled (the resulting OFFSET is 0 and the bit is still set); the input pair floating vs. held at mid-supply by VBIAS; unipolar vs. bipolar supplies; whether we read registers while the calibration runs.
- The calibration doesn't change the channel's DATA_PER_CHANNEL register. STATUS CH_ACTIVE reads 0 afterward, while a single conversion on the same channel leaves it at 3.
Two related observations
- A second calibration triggered straight from the idle state the previous one leaves (writing MODE 1010 again with nothing in between) never completes: RDY stays high for more than 2 s. Writing ADC_CTRL = idle and rewriting CHANNEL_EN before each calibration avoids this.
- With FILTER set to Sinc3 (0x0006) and FILTER_FS 5000, ADC_CONV_ERR was set during continuous conversion of the shorted input. We saw this once and haven't investigated further.
Questions
1. Is ADC_CONV_ERR expected at the end of an internal or system zero-scale calibration? If so, what does it indicate?
2. Can the OFFSET produced by the calibration be trusted when the bit is set? Is there a recommended way to confirm that a calibration succeeded?
3. Is it required to re-enter idle and rewrite CHANNEL_EN before each calibration? Is this documented anywhere?
We can share register dumps or logs if helpful. Thank you!
