Dear All,
I have been working on this design (a CCD with an AFE and an ADC) for a while and I am now at the stage where prototype PCBs have been made (still waiting to receive them), which I will soon begin testing with.
I was going through the datasheets the other day dreading that I might have missed something and then it hit me:
The entire AFE and ADC might not be compatible with the CCD which I am using.
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The question:
Please let me know if the AD9826 when used in CDS mode can handle a voltage swing of (a maximum of) 3V from a value (reset level) that is lower than 18V to a value (signal level) that is higher than 12V.
Urgent help is needed and would be appreciated.
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Note that the range for Vout for the S9970-1006 is 12V to 18V as stated in the S9970's datasheet.
Note also that the AD9826 can be configured to have a 0-3V or 0-4V input range (In CDS mode the reset level gets clamped to 3V or 4V respectively) as stated in the AD9826's datasheet.
The question is therefore: How high is the reset level (at the output of the unity gain op-amp) allowed to be, before the AD9826's CDSCLK1 pulse occurs (Clamping happens during this pulse).
Please also note the "ABSOLUTE MAXIMUM RATINGS" table for the AD9826.
I have attached a screenshot of the KiCad schematic of the configuration.
Here is a link to the datasheet for the S9970: https://datasheet.sisoog.com/file/7a657573/datasheet/a6d9c62a85df86dbe9061d3c6cf77d5f1a36db54.pdf
The datasheet for the AD9826 is available from analog devices.
