Subject: AD4130-8 — IEXC/VBIAS behavior during falling common AVDD/IOVDD rail and POR
I am using an AD4130-8 LFCSP in a high-impedance DC voltage measurement application.
AVSS = DGND = 0 V. AVDD and IOVDD are tied to the same nominal 3.3 V rail, so they rise and fall together.
AIN0 is connected to an approximately 9.44 MΩ / 10 kΩ passive divider, with 47 nF from AIN0 to AVSS. AIN1 is tied to AVSS.
During normal operation:
- I_OUT0_n = OFF
- I_OUT1_n = OFF
- BURNOUT_n = OFF
- VBIAS on AIN0/AIN1 = OFF
- STBY_IEXC_EN = 0
- STBY_VBIAS_EN = 0
- STBY_BURNOUT_EN = 0
- SPI is configured for 4-wire operation
- FIFO is disabled
- CONT_READ = 1
- DIN is held LOW during normal continuous-read operation
I am trying to prove safe behavior during abrupt or slow loss of the common 3.3 V AVDD/IOVDD supply.
The datasheet states that a POR occurs when IOVDD or the digital LDO falls below its specified operating range, and that POR resets the user configuration registers. CONFIG_n, VBIAS_CONTROL and MISC reset to states in which IEXC, VBIAS, burnout and their standby-retention enables are OFF.
Could you please clarify the following:
- With CONT_READ = 1 and DIN held continuously LOW, is it guaranteed that no sequence of CS/SCLK activity can modify a configuration register or enable IEXC/VBIAS/burnout unless Continuous Read is first exited using one of the two documented mechanisms (0x42 while data-ready is low, or the 64-one software reset)?
- During a monotonic or abrupt fall of a common AVDD = IOVDD rail from 3.3 V toward 0 V, are IEXC0, IEXC1, VBIAS and burnout outputs guaranteed to remain in their programmed OFF states until POR/reset forces their default OFF states?
- Is there any interval during falling supply—particularly between the minimum specified operating voltage and POR assertion—in which the user configuration registers or the IEXC/VBIAS output controls can become indeterminate or briefly enable/glitch even though they were programmed OFF beforehand?
- Can you provide the guaranteed falling POR assertion threshold (min/max if available) and maximum POR assertion delay for IOVDD/digital-LDO undervoltage?
- When POR asserts, are the IEXC/VBIAS/burnout analog outputs forced OFF immediately/asynchronously, or only after the register-reset/initialization sequence completes? Does
tRESET_DELAYhave any relationship to analog-output disable timing, or is it only the delay before subsequent SPI access?
The reason for the question is that the external AIN0 node contains 47 nF. If an excitation or bias output could momentarily become active during brownout, that capacitor could retain voltage after AVDD falls and potentially challenge the AIN ≤ AVDD + 0.3 V absolute-maximum requirement.
I am specifically trying to determine whether the combination of safe programmed state + Continuous Read/DIN LOW + common AVDD/IOVDD POR makes that condition unreachable, or whether an external discharge/clamp is still required.
Thank you.
