CLKCON0 (SYSCLKDIV) write not persisting

Here's an AI summary (sorry) of the problem we are facing.

AD5941: CLKCON0 (SYSCLKDIV) write not persisting — clock-register region reads garbage while neighbours are fine.

Setup: AD5941 (CHIPID 0x5502), STM32H7 host over SPI (mode 0, ~12 MHz), internal HFOSC only (no HFXTAL). Running impedance sweeps.

Low-speed mode (16 MHz HFOSC, 800 kSPS ADC) works perfectly — full sweeps complete. High-speed mode (32 MHz HFOSC, 1.6 MSPS ADC) fails.

Symptom in high-speed mode: the first sweep point measures correctly and returns valid DFT data, then every subsequent point produces nothing. The sequencer keeps running and the ADC keeps converting, but no DFT results are ever produced and the FIFO never fills, so no data-ready interrupt fires.

What we measured (SPI register readback):

• CLKCON0 (0x0408): writing 0x0042 (SYSCLKDIV=2, ADCCLKDIV=1) lands once right after a clean wake (reads back 0x42), then reads back 0x00 on the next write and stays there — it never persists.
• CLKSEL (0x0414): reads 0x00.
• CLKEN1 (0x0410): reads 0x00 in steady state.
• HPOSCCON (0x20BC): reads back 0x5502, i.e. the CHIPID value — a read of a clock-region register returning an unrelated register's contents.
• Neighbouring registers written over the same SPI in the same session hold perfectly: DFTCON (0x20D0) = 0x1000A0, ADCFILTERCON (0x2044) = 0xC010, PMBW (0x22F0) changes from reset as expected.
• HFOSCOK reads 1 immediately after the 32 MHz switch, then 0.

We've confirmed the divider-before-oscillator ordering (write SYSCLKDIV=2 while still at 16 MHz, then switch HFOSC to 32 MHz), correct SPI framing/CS timing, and slower SPI clock — none change the behaviour. Because SYSCLKDIV=2 never sticks, the digital die appears to run overclocked at 32 MHz, which is consistent with the ADC-rate→DFT ingestion being dead while everything else runs.

Question: Has anyone seen an AD5941 where the clock registers (CLKCON0, CLKSEL, HPOSCCON around 0x0408 and 0x20BC) go bad like this — writes just don't stick and reads come back as some other register's value — but everything around them works fine? Low speed is rock solid so the part isn't dead. Before I write this chip off, is there any lock bit or enable sequence on CLKCON0 I might be missing, or does this look like a fault in the part?

Raw readback from a high-speed sweep attempt (steady state, repeats identically ~1/s):

seq keeps counting and adc keeps changing (sequencer + ADC alive), but clkcon0/clksel/clken1 read 0, hposc reads 0x5502 (the CHIPID), while dftcon/filt hold correct values. dft and fifo stay 0, so no result is ever produced.