Hello,
I'm attempting to port your AD4080FMC eval board HDL design from a Zedboard to a Genesys ZU Ultrascale+ carrier. With your Zedboard design and VADJ set to 2.5V the data looks perfect but with our Genesys ZU ported design the data is just noise. Digital bring-up is complete: LVDS alignment, SPI configuration and data capture all work, and we get sustained conversions at our target rate, the analog path, however, reads essentially nothing..
We bisected the chain with the source verified live at each reading
(256 Hz, ~60 mV RMS):
Card inputs TINP / TINM ................. 32 mV each
Stage 1 out (LT6236, R10/R11) ........... 62 mV differential
Stage 2 out (ADA4945-1, P2 pins 1/7) .... 62 mV differential
Stage 3 out (ADA4899-1 A1/A6, R104/R105) .... 0 mV
ADC input (R32/R88) ......................... 0 mV
Stage 3's operating conditions all measure correct: S1-3 is OFF (enabled
per Table 4), A1/A6 pin 7 = 5.0 V, and ENS3 at A1/A6 pin 8 = 1.8 V.
Our reading is that the last item is the fault. The ADA4899-1 data sheet
specifies the DISABLE input threshold as "output disabled, < 2.4 V",
referenced to ground. ENS3 is driven by U28, a TC7S08 whose VCC is
FMC_VADJ, so ENS3 can never exceed VADJ. On the ZedBoard with J18 in the
2V5 position (UG-2214 setup step 3) that is 2.5 V and the amplifiers
enable, with roughly 100 mV of margin. Our carrier's FMC LVDS pins are in
a Zynq UltraScale+ HP bank, limited to VCCO <= 1.8 V, so VADJ cannot be
raised. ENS3 sits ~600 mV below threshold and Stage 3 remains in
high-impedance shutdown.
Questions:
1. Is that analysis correct - is Stage 3 expected to be non-functional on
any carrier supplying VADJ below approximately 2.4 V?
2. UG-2214 gives the 2.5 V VADJ requirement as a ZedBoard setup step. Is
the evaluation board intended to be usable on 1.8 V VADJ carriers at
all? Many FMC carriers built around UltraScale+ HP banks cannot exceed
1.8 V.
3. We are considering removing U28, which leaves ENS3 unconnected. The
ADA4899-1 data sheet states that "when the DISABLE pin is left floating
(open), the ADA4899-1 operates normally", and on this board ENS3 has no
other loads and no pull-up or pull-down. Is that an acceptable
modification? In particular, is there any concern with two ADA4899-1
DISABLE pins tied to each other and floating, rather than one pin
floating in isolation?
4. Is that preferable to the documented Stage 3 Bypass (UG-2214 p.16)? We
would rather not bypass, since it forfeits Stage 3's distortion
performance.
Thanks for the help
Scott
