EVAL-AD4080-FMCZ: Stage 3 (ADA4899-1) cannot be enabled on a 1.8 V VADJ carrier — expected?

Hi DomSloan ,

Could you please help look into this query?

Thanks,
Francis

Hi Scott,

          Unfortunately the EVAL-AD4080-FMCZ was designed for a 2.5V VADJ. I am surprised that the LVDS alignment has worked with VADJ = 1.8V, as AD9508 would not be getting the correct supply. 

1.         Yes, your analysis is correct, ADA4899-1 would require its DISABLE_N pin to see <2.4V to get enabled, so it is likely the issue you are seeing is caused by having V_ADJ at 1.8V
2. The board was designed for a 2.5V VADJ carrier, to be honest, I'm not sure we had considered that this level may not be provided by some carriers. Unfortunately though FMC_VADJ supplies some other housekeeping circuitry also, that may not operate correctly at 1.8V, e.g. U9 that manages some of the power up sequence, and also powers the AD9508 clock buffer/divider as well as the level shifters for the SPI and GPIOs. AD9508's min supply is 2.375V.
3. That would work for the ADA4899-1 but the issues in 2. would not be resolved.

Rgds,

Dom

Hi Dom,

Thanks - that confirms our analysis. We'll treat the EVAL-AD4080-FMCZ as
a 2.5 V VADJ board.

Context: we're building a 16-channel, 20-bit synchronous system at 4-5
MSPS/channel. That's ~1.3-1.9 Gbps continuous, which rules out the
ZedBoard's 1 GbE, so we're on a Genesys ZU-5EV (XCZU5EV) for its SFP+ 10G
- currently measuring ~2.6 Gbps sustained over TCP. The FMC LVDS pins
land in UltraScale+ HP banks, which are limited to VCCO <= 1.8 V, so 2.5 V
VADJ isn't available to us on this class of carrier.

Three questions:

1. 16-CHANNEL CARD AT 1.8 V VADJ
We plan a custom 16 x AD4080 FMC card, using VADJ only to match FPGA I/O
level for level translation, and generating all analog, clock and enable
rails on-card from FMC +12 V and +3.3 V - avoiding both 2.5 V
dependencies on the eval board. Do you see any obstacle to that? And can
you confirm the SPI/config lines (DCS, DCLK, GPIOx, SDOx) must be level
shifted down from 1.8 V, given IOVDD absolute maximum is +1.26 V? We also
plan to drive CNV in LVDS mode (LVDS_CNV_EN = 1) - is that recommended
for multi-chip use?

2. SYNCHRONISING 16 AD4080s
We intend to share one CNV and one CLK, fanned out with matched skew to
all 16 devices, budgeting against tCCA = 535 ps. Is that the approach you
would recommend, and is there an ADI reference design or app note for
multi-chip AD4080 synchronous operation? Specifically: does the on-chip
digital filter require phase alignment across devices, or is a common CNV
sufficient - and if not, what sync or reset sequence aligns them?

3. WOULD THE AD4880 BE A BETTER FIT?
Eight AD4880 would give us 16 channels and remove the entire discrete
front end. Would you recommend it over 16 x AD4080 for this application?
Is the EVAL-AD4880-FMCZ also a 2.5 V VADJ design? How does
synchronisation work across multiple AD4880 devices? And since it's
described as optimised for inputs up to 1 MHz, how much do we give up
above that - our band extends toward Nyquist at ~2 MHz?

Question 2 is the most urgent, as the synchronisation approach determines
the daughtercard clock tree.

Thanks,

Scott

Hi Scott,

           I see the Zeboard limitation there and think you are taking the correct approach, I think for future boards I will also be avoiding the VADJ dependency for any housekeeping circuitry.

1. LVDS CNV for multi-chip use is quite a common use case, and we can make some recommendations for the clock tree, such as in the block diagram below. There are quite a few different approaches that could be take, parts such as ADCLK846, ADCLKK944 are aslo suitable candidates. The HMC7043B has 14 output pairs, though the minimum input clock is >400 MHz so moving to 800 MHz input would be suggested there.
2. Yes, this is the approach we'd recommend, the digital filter can be reset/synchronized using any GPIO configured as a FILTER_SYNCB input, the timing of this is described in figure 98 of the datasheet.This would be recommended across multiple devices if synchronization is required, as it may be easier to do this via GPIO pin control rather than trying to synchronize the SPI commands to 16 devices, where the SPI may be asynchronous to the CNV etc.
3. The EVAL-AD4880-FMCZ is also a 2.5V VADJ design. Its suitability really is down to the nature of the input signal and the performance you are tying to target. Figures 32, 33 and 34 of the datasheet (currently Rev0) give some indication of how the performance will begin to degrade as you increase the input frequency. This is predominately limited by the slewing of the integrated driver, and as you can see with reduced input swings will then be affected less.

   Rgds,

   Dom

Sounds good, thanks for all your help Dom.

Scott

No problem!