AD7124: Temporary offset transient after channel reconfiguration, fully recovering over time

Hello Analog Devices Support Team,

I am working with the AD7124 and I am observing a repeatable behavior when reconfiguring the ADC between two measurement modes. I would like to ask whether this behavior is expected for the AD7124 architecture and what the recommended mitigation is.

Measurement setup

• ADC: AD7124
• Reference: same reference for all measurements (no change during reconfiguration)
• Continuous operation
• No external input switching during the critical measurement (input is shorted to 0 mV)

Measurement modes

1. Mode A (primary mode)

   • Continuous measurement of a very small DC signal (order of single mV)
   • High sensitivity setup
   • This mode runs for long periods and requires good offset stability

2. Mode B (secondary mode)

   • Occasional, one‑shot measurement on different input pins
   • Originally ~900 mV, but I verified that even a few mV produce the same effect
   • After the measurement, the ADC is reconfigured back to Mode A

Observed behavior

After returning from Mode B back to Mode A:

• A temporary offset shift appears in Mode A, even when the input is shorted to 0 mV
• The offset shift:
  • has a fast onset immediately after reconfiguration
  • relaxes slowly over time (seconds)
  • fully returns to the original value without intervention
• The behavior is independent of signal amplitude (same effect for 900 mV and 3 mV)
• Changing PGA settings does not eliminate the effect
• Enabling/disabling input buffers does not change the character of the offset transient
• Standard settling time after reconfiguration is already respected
• A soft reset is performed before each reconfiguration, but this does not prevent the transient

I have attached a plot showing the transient behavior at 0 mV input, where a distinct negative offset transient appears and then slowly returns to the nominal level. 

Preliminary conclusion

Based on testing, this looks like a temporary internal analog offset / bias drift caused by reconfiguration, rather than:

• input settling
• reference instability
• PGA saturation
• digital filter settling only

Questions

1. Is this temporary offset transient after reconfiguration an expected behavior of the AD7124 due to its shared analog front‑end / bias architecture?
2. Does the soft reset reset only the digital state, leaving internal analog offset/bias circuits unaffected?
3. Is there a recommended sequence to minimize this effect when switching between channels or measurement modes (e.g. dummy channel, standby/power‑down, offset calibration, discarding samples)?
4. Would you recommend using:
   • a short dummy conversion on a grounded channel, or
   • SYSTEM OFFSET CAL after returning to the sensitive measurement mode?
5. Is there any application note or errata that discusses this behavior for AD7124 or similar Σ‑Δ ADCs?

Thank you in advance for your guidance.

Best regards,