ADC digital output not reflecting analog input voltage

We are using LTC2311-12 ADC in our design to sample SOC voltage periodically and the digital data is fed to FPGA externally. 

Below are the details of design implementation for this ADC,

1. Analog input to ADC: 0V to 3V - Pseudo differential unipolar (LT1807 precedes analog inputs of this ADC)
2. ADC resolution: 12 bit
3. VDD supply: 5V
4. OVDD supply: 1.8V
5. Mode of operation – digital output: CMOS

1. 1. ADC digital output SCK clock is generated by FPGA (105MHz)

1. REFOUT and REFIN: Internal to ADC is used
2. CNV pin: Is fed from an FPGA via D-flip flop implementation (Similar to LTC2311-12 reference schematics.  D-flip flop clock (105MHz) is generated by FPGA (low jitter source))
3. Sampling frequency: 5Msps (105MHz)

Issue observed:

We see that ADC does not convert the analog input voltage accurately.  Despite analog input voltage varying dynamically, the digital output remains stuck at 7F (2’s complement).

We did try reducing the sampling frequency to 50MHz.  Even with this, the digital output remains the same.

All the power supplies to this ADC (VDD, OVDD, REFOUT, REFIN) measured were clean and well within the electrical specifications.

Can you please let us know what could be possible reasons for ADC digital output not changing w.r.t analog input voltage?

Your quick response for this issue is highly appreciated.  Please let us know if you need any more information.

Waveform captures:

105MHz sampling frequency:

50MHz sampling frequency:

Regards,

Archana Rao