Sampling synchronously, FPGA host to 3 AD4052 ADCs

Hi,

  will look into this and get back to you.

Warm regards,
Jo

Any news?

Do you know when RRED will be available to answer?

Regards

Hello Slir, 

you really don't find the PCB-space for a small damping resistor?

slir said:

1. Should we still add the SCLK series resistor?

Your length differences on SCLK are completely uncritical. SCLK is no timing critical signal (in contrast to CNV) as the maximum frequency on SCLK is anyhow limited to 33MHz. You only have to care on the signal integrity, i.e. the form of the edges on SCLK at the ADCs input. 

slir said:

2. If we don't place the resistor, how will it affect?

If you would have no damping at all, SCLK would be affected by ringing. See the simulation below, where V1 is the FPGA pin driving SCLK, C1..C3 are the capacitances of the ADCs SCLK input and the transmission lines represent the striplines on your PCB.

Without any real damping (Rdamp set to 1 Ohm) you would see critical ringing. With Rdamp = 33 Ohm or Rdamp = 100 Ohm the edges are fine for the demands of SCLK. 

So some damping is required. But fortunatelly the FPGA driver is no "perfect voltage source" as V1 in the simu, but has anyhow some damping included. Check the datasheet of your FPGA for the drive characteristics. Probably you can influence the driver settings (e.g. for reduced slew rate or for week driver strength) to optimize signal integrity. 

best regards

Achim