Hello,
I am working with the AD7328 ADC in an SPI interface, and I need clarification on the timing specifications related to DOUT.
In the datasheet, t₄ (SCLK falling edge to DOUT valid) is specified as 43 ns (max). At the same time, the device supports an SPI clock frequency up to 20 MHz (SCLK period = 50 ns), but im using 12.5 MHz spi clock
My confusion is:
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At 20 MHz, the next rising edge of SCLK occurs after 25 ns. This is earlier than the maximum t₄ = 43 ns, so in the worst case, the data may not yet be valid when sampled at that edge.
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Does this mean that at 20 MHz the system is expected to sample DOUT at a later point in the cycle (e.g., on the falling edge, or with a shifted clock), rather than directly on the rising edge?
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Or should we rely on the typical t₄ values (which are faster than 43 ns), meaning the “20 MHz max” spec assumes that in practice DOUT will usually be valid in time?
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Could you clarify the recommended way to reliably sample DOUT when operating at 20 MHz, given these timing numbers?
- And also want to clarity of differentiation of t4 and t7 timings
Thank you for the guidance
