SYNC_IN to first DRDY time

Hi JoeSe ,

Please refer to the answers below and let me know if you have other questions.

Q1.The SYNC_IN to DRDY time is computed as 3/ODR for sinc3 and 5/ODR for sinc5

I am in the process of correcting the datasheet to 188 uS for this value. Please refer to the calculation below

for ODR = 16kSPS

tinit = 3/(16k) = 188 uS

Q2. Yes. This time should be relatively stable.

Q3. The sync signal is delayed by the value written in the CHx_SYNC_OFFSET registers 

is added to the 3 ODR settling time

Q4. Typically, these registers are used to match the phase of multiple channels and compensate for delays. The channel with the biggest delay is used as the reference and the difference from the other channels is written to the registers as discussed in these links

AD777x: What is the best phase offset calibration process? - Documents - Precision ADCs - EngineerZone

AD7771 Phase Adjustment Question - Q&A - Precision ADCs - EngineerZone

ad777x phase adjustment - Q&A - Precision ADCs - EngineerZone

To add a phase delay per channel, please refer to the steps below.

ODR = 16kSPS; dec_rate = 128 MOD Clk = 2.048MHz

Compute for the delay in Mod cycles

delay = 20uS/(1/2.048MHz) = 20uS * 2.048 MHz = 40.96 cycles ~= 41 cycles

Register value = (dec_rate - mod cycles)/Phase Adjustment compensation = (128-41)/1 = 87 = 0x57

for delay of 50uS

delay = 50uS * 2.048 MHz = 102.4 ~= 102 cycles

Register Value = (128-102)/1 = 26 = 0X1A

Thanks,
Janine

Hello Janine!

Thank you for your fast reply.

To Q1:

I have measured the time between rising edge of SYNC_IN and the rising edge of the first DRDY pulse. I always measure 142.2 us with my ADC settings (MCLK=8.192 MHz, Decimation Rate 128, ODR=16 kSps, High Resolution Mode, all CHx_SYNC_OFFSET unwritten).

If I write the value 127 to all CHx_SYNC_OFFSET registers, the time changes from 142 us to 204 us. This is exactly the 62 us delay I expect.

But how to get 3/ODR = 188 us? 

to Q4:

As I understand your answer, there is no chance to delay ALL channels by given delay values in the CHx_SYNC_OFFSET registers. The channels can only be delayed relative to each other.The one channel (for example CH0) with the biggest delay remains undelayed (CH0_SYNC_OFFSET=0), the other channels will be delayed until they match CH0?

thanks a lot for your support

Sebastian

Hi JoeSe ,

Please refer to the answers below.

Q1. 142 uS is correct. I apologize for the confusion. 188 uS is the estimated settling time of the sinc3 filter.

If you are able to get the 62 uS, the offset register is indeed working as expected.

Q4. There is a chance to delay all channels by using the offset registers, but this is not the usual case for the phase offset adjustment.

The usual use case for this is to use one channel with the highest delay and set it as the reference and delay the other channels to maintain phase coherence between the channels.

I hope I have clarified your confusion. Let me know if there is anything else.

Thanks,
Janine

Hi JoeSe ,

Please refer to the answers below.

Q1. 142 uS is correct. I apologize for the confusion. 188 uS is the estimated settling time of the sinc3 filter.

If you are able to get the 62 uS, the offset register is indeed working as expected.

Q4. There is a chance to delay all channels by using the offset registers, but this is not the usual case for the phase offset adjustment.

The usual use case for this is to use one channel with the highest delay and set it as the reference and delay the other channels to maintain phase coherence between the channels.

I hope I have clarified your confusion. Let me know if there is anything else.

Thanks,
Janine

Thank you Janine!

All my questions are answered now.

bye

Hi JoeSe ,

I am glad to hear that.

Please feel free to post another query in the forum link below if you happen to have any other issues.

Q&A - Precision ADCs - EngineerZone

Thanks,
Janine