Data Interface no valid Data from AD4858

Hi, opi .

 will look into this and get back to you.

Regards,
Jo

Hi opi  

Let me check this and get back to you shortly.

Thanks,

Red

Hi Red

would be great if you have a look at my problem

thanks

otmar

Hi Nathan

Unfortunately Red did not answer

The problem is the busy signal from the chip

i don't know why the chip set the busy line to high during reading data...

Actual we wanted to use this chip in our new design .....

Sadly we bought an expensive starter Kit together witch the ZEDBoard which is now useless

I also examine the lines between startkit  and Zedboard - and the timing is other then denoted in the datasheet

for example on the Zedboard the nCS line is always low

Perhaps you had any idea to the strange behavior of the busy line

Hi Otmar,

Yes, that does not make sense to have BUSY toggling so frequently. It should only toggle once when a CNV pulse is received, and stay high for as long as the conversion time (around 665ns).

Is BUSY toggling at the same frequency as SCLK? What is the SCLK frequency? Is there a chance that your SCLK signal being coupled into either CNV or BUSY?

These scope shots you sent are by using the Nucleo board? If so, and you also the zedboard, can you also try to connect ACE to the EVAL-AD4858FMCZ just to verify the devices works well with the ACE software provided?

Thanks,

Lluis.

Hi LIuis

thanks for your answer

I assume also a crosstalk from SCLK to CNV. To check this i added a Pullup at the CNV and BUSY Port  on my Testboard.

The result was a lower "BUSY acitvity" during Data reading but not completely gone...

Yes the scopes were from my Nucleo Board.

I have an scopc from the signals on the zedboard and the EVAL Board - there  the comunication works but looks "very interesting"

The timing is different than in the datasheet described

The CS line (brown) is always 0 - i thought the CS line must always be enabled/disabled?

The CONV signal is set during Data communication - is this ok?

The signal lines  (CONV, BUSY, SCLK, ...) on the EVAL are very long and all are in parallel - predestinated

for coupling

So make it sense to design a own board with the AD4858 and my STM controller where the signal paths are short?

What do you think?

thanks

kind regards

otmar

Hi opi 

Were you able to solve the issue ?

We are facing a similar problem:

• The SDOx lines always return garbage data
• The BUSY line shows parasitic toggling activity where none should be present

Could you confirm whether your issue was linked to the parasitic activity on BUSY, or was that only a side effect of another root cause ?

Best regards

Hi PiR

Not yet, but I am working on it.

I guess (and also hope) the problem is the layout of the evaluation board. Because the tracks of the signal are close to each other. If you use the LVDS interface this wont be a problem. So I have designed a new board.  This is now in production and will be finished in 2 weeks - then i can say more when i have tested the board

best regards

Hi opi,

Thank you for your feedback.

I have spent some time investigating this issue on my side. I am using the AD4853 instead of the AD4858, but the symptoms are very similar, and since these devices belong to the same family I believe my findings could also apply to your case.

In my setup, there was indeed crosstalk between the SCKI and CNV signals. At each SCKI rising edge, a voltage spike of about 820 mV appeared on the CNV line. This is just enough to trigger a new conversion, since the threshold is 800 mV (according to the datasheet). This occurs systematically on rising edges. The falling edges sometimes produce smaller spikes, but less consistently.

The garbage data observed on the SDOx lines turned out to be the result of conversions being unintentionally retriggered. You can see this clearly on an oscilloscope because the duration of each SDOx bit becomes inconsistent, while a logic analyzer (at least mine) does not show this behavior clearly.

A solution I found is adding a 470 Ohm series resistor directly next to the ADC on the CNV trace (I have not tuned the exact value yet). This slows down the CNV signal and reduces the crosstalk amplitude to just a few dozen millivolts. It works reliably while still allowing CNV pulses that are shorter than the BUSY pulse. Maybe Lluis or someone from ADI could confirm whether this is recommended or not ?

Adding a pull-down resistor on either SCKI or CNV did not resolve the issue, this is consistent with what you mentioned earlier.

As for the origin of the crosstalk, it is quite interesting. It seems to come from the ADC itself. Disconnecting the SCKI wire from the ADC (while keeping it connected to the MCU) eliminates the spikes entirely, so the master is not the source. With the 470 Ohm resistor in place, even with long wires and in particular CNV and SCKI wires parallel and close to each other show no coupling issues.
Perhaps ADI could comment on this behavior as well?

I hope these observations help.
Best regards

Hi PiR

thanks for your detailed answer.

Did you also use the evaluation board?

In my current there is place for a LP Filter in each data line, to reduce the harmonics - if necessary...

I am confident my board works, when you overcome the problem with  470R in series. I will give feedback as soon as possible

best regards

opi