Sharing of SPI lines with AD4112.

Hi DespicableMe ,

Yes, it is okay to share SPI lines with two AD4112. May I know how do you plan to read the data between the two ADCs? Do you plan to synchronize the ADCs conversion?

Regards,

JC

Hi JCCillion ,

Thanks for the reply.

Yes I am planning to read by synchronizing the ADC conversion.

Hi DespicableMe ,

You may simplify the interface when using multiple ADCs by using the /SYNC pin to synchronize the devices. When using the Alternate Synchronization, you may be able to control the instant at which the conversion begins on the next channel. For Normal Synchronization, when SYNC pin is low, the modulator and digital filter are in reset and an input rising edge on the SYNC will remove the modulator and filter out of the reset state and the device starts to gather input samples again on the next main ADC clock edge. The devices must be sharing the same CLKIO or the clock from a main ADC can also be used as input to the other subordinate ADCs. You will then need to monitor only the DOUT/RDY signal of the main device. When the DOUT/RDY goes low, read its conversion. At this point the other ADC has already completed converting. Since they are in sync, it is not necessary to monitor the DOUT/RDY signals of the other ADC. With this connection, it is important that all conversions from the ADCs are read back before the next conversion of the main ADC is read. This ensures that all conversions from the ADCs are read (ensures no conversions are missed).

Regards,

JC

Hi JCCillion ,

Thanks for the explanation. I have few doubts:

1. When using SYNC mode should the SYNC pin be pulled-up by default?

2. When 2xAD4112 devices are used, then the DOUT/RDY pins of the two devices can they be monitored by single MISO pin?

Hi JCCillion ,

Thanks for the explanation. I have few doubts:

1. When using SYNC mode should the SYNC pin be pulled-up by default?

2. When 2xAD4112 devices are used, then the DOUT/RDY pins of the two devices can they be monitored by single MISO pin?

Hi DespicableMe ,

1. Yes, the SYNC pin should be pulled-up by default. This is to ensure that the ADC's modulator and digital filter are not in reset.

2. Yes, only a single MISO pin can be monitored if the ADC is synchronized and has the same configuration. The ADCs would have the data ready at the same time so it is okay to just monitor a single MISO line.

Regards,

JC

Hi JC,
Refer attached image, is my configuration ok? My doubt here is can I connect the DOUT of 2xAD4112 together and give it to microcontroller?

Hi DespicableMe ,

Your configuration is okay. Note that the /CS pin of the other ADC is high while communicating to one of the ADC. Taking /CS high disables the serial interface of the ADC so it ignores any activity on the data bus.

Here is an FAQ that may be of use to you.

(+) How do I interface to multiple ADCs over the same serial interface? - Documents - Precision ADCs - EngineerZone

Hope this helps.

Regards,

JC

Thanks JCCillion . This is helpful.

Hi JCCillion ,

With the above configuration as shown in the image, both ADC are not working. When CS is LOW, the DIN, SCLK and DOUT/RDY pin are always HIGH. If I don't connect the ADCs, I can see output from the microcontroller on the scope. After connecting back the ADCs all signals go HIGH.

Hi DespicableMe ,

Could you confirm if the ADC is powered on correctly? Please try connecting 1 ADC at a time to simplify the debugging. What is the voltage measured at AVDD, IOVDD and REF+?

DespicableMe said:

I can see output from the microcontroller on the scope

The SPI lines pass through the isolator, could you also probe in the ADC side of the isolator and see if the serial interface is communicating correctly. For example, try reading the ID register of the ADC and see if it gives the correct ID.

Regards,

JC

Hi JCCillion ,

The ADC is powered up correctly. I slightly modified the configuration as attached and make "ADC1 CS LOW" and "ADC2 CS HIGH", ADC1 is detected I can see SPI CLK and DATA at the ADC pins.

When I make "ADC1 CS HIGH" and "ADC2 CS LOW", then ADC2 is not detected and does not work. No SPI CLK and DATA observed at the ADC2 pins. Is there any configuration I am missing?

Hi DespicableMe ,

This is a bit tricky to debug as there is an isolator between the ADC and the MCU. When you say that there is "No SPI CLK" where are you probing this SCLK? Are you probing in the MCU side or the ADC side? The SCLK signal is input to the ADC and is provided by the MCU so it is possible that the MCU is not communicating properly with the ADC2 resulting to no DATA observed.

During proper operation, the SPI signals sent from the MCU side should of the same on the ADC side. Could you confirm this?

For ADC2, upon power-up pull /CS low and verify if the DOUT/RDY pin is pulsing at the default ODR. This will help confirm that the ADC is powered up and is converting at the default ODR.

Regards,

JC

Hi JCCillion ,

Let me explain again:

Condition 1 -  ADC1 CS LOW and ADC2 CS HIGH

1. SPI CLK : Clock observed at MCU and ADC1 pin (16)

2. SPI DATA (MOSI): Data observed at MCU pin and ADC1 pin (15)

3. SPI MISO : Data observed at MCU and ADC1 pin (14).

Condition 2 - ADC1 CS HIGH and ADC2 CS LOW

1. SPI CLK : Always HIGH (5V) at MCU and ADC2 pin (16)

2. SPI DATA (MOSI): Always HIGH (5V) at MCU pin and ADC2 pin (15)

3. SPI MISO : Always HIGH at MCU (5V) and ADC1 pin (14).

I don't understand why all signals go HIGH during Condition 2.

For ADC2, upon power-up pull /CS low and verify if the DOUT/RDY pin is pulsing at the default ODR. This will help confirm that the ADC is powered up and is converting at the default ODR.

Reply: This I will check.

Hi JCCillion ,

I am able to get data on the Data and clock lines, the issue was with the pull-up resistor. But one doubt, what is the minimum time delay to be maintained for Chip Select pin when switching between ADCs?