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The AD7779 is an 8-channel, simultaneous sampling ADC. There are eight full Σ-Δ ADCs on chip. The AD7779 provides an ultralow input current to allow...
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Synchronise sampling on an interrupt manage by a µC

		
	
				

			

									
					    Martial73
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Apr 14, 2025 
				
			
			
		
    
		
		                    	    
    
        	    
    Thread Summary
    
                The user is trying to synchronize sampling on the AD7779 ADC using an interrupt managed by a microcontroller. The issue is that DRDY pulses do not appear after issuing a sync pulse via the START signal or SPI_SYNC bit. The support engineer suggested checking the configuration of bit 4 in register 0x5F and ensuring a reset pulse is issued after power-up. The user confirmed the ODR is set to 5kHz and will test the SPI_SYNC bit.
                        	    
    
                
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    Category: Datasheet/Specs
    
    		        		            		    
    Product Number:  AD7779  
    
    		        		    		    
    
		    		    
		    			
    
			    
    Hello,
    

    Currently, I used an AD7779 with following configuration:
    

      

    • Sigma-Delta mode,
      • 

    • Sampling each 200µs.
      • 

    

    I would like to synchronise sampling on an interrupt manage by my µC as you can show on the following picture:
    

     
    

    So is it possible to do this treatment ? If yes, could you tell me how ?
    

    For information, in my application SYNC_OUT and SYNC_IN are linked. I have tried to synchronise sampling using START signal on the interrupt but when I do this, DRDY never come.
    

    Thanks in advance.
    

    Best regards,
    

    Martial
    
			
    
			
									
		                             
                        

    
    
                                            
                 synchronized sampling
                
                                                    
                 Datasheet/Specs
                
                                                    
                 ad7779
                
                                                    
                 Simultaneous Sampling A/D Converters
                
                                                    
                 Precision A/D Converters
                
                                
            
    
    
    
		
    

				
				        
        		
    
			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		
    

        
        
        
    
					
    
			
    


    
















    
	
    
	
    
					



			








	
	
	
	



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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Apr 16, 2025 12:58 AM
            
            
						
			            		
      
		
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      Hi  ,
      

      Do you want the samples to be available every 250 uS or ODR = 4kHz?
      

      Can you also clarify what "IT Start sampling" means in the figure?
      

      Whether you apply the sync pulse through SYNC_IN, START, or by writing to SPI_SYNC bit, there should be DRDY pulses after.
      

      There should be DRDY pulse upon power up. Can you try writing to SPI_SYNC bit?
      

      Please share the schematic and register settings.
      

      Thanks,
      Janine
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Apr 16, 2025 12:58 AM
            
            
						
			            		
      
		
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      Hi  ,
      

      Do you want the samples to be available every 250 uS or ODR = 4kHz?
      

      Can you also clarify what "IT Start sampling" means in the figure?
      

      Whether you apply the sync pulse through SYNC_IN, START, or by writing to SPI_SYNC bit, there should be DRDY pulses after.
      

      There should be DRDY pulse upon power up. Can you try writing to SPI_SYNC bit?
      

      Please share the schematic and register settings.
      

      Thanks,
      Janine
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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                on Apr 16, 2025 12:19 PM
            
            
												
						in reply to JEstayo
					
										
			            		
        
		
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        Hello Janine,
        

        Thank you for your reply.
        

        I set my ODR at 5kHz to have a DRDY pulse each 200µs. I'm not sure to understand the difference between samples available every 250µs and ODR = 4kHz. Could you explain to me ?
        

        "IT Start sampling" => IT = µC interrrupt and Start sampling = pulse to 0V on START signal
        

        Here a new figure to explain what I try to do:
        

         
        

        I will try writing to SPI_SYNC bit to see the behavior (maybe Friday, because I can't work on this subject before). 
        

        Below is the schematic:
        

         
        

        I will send you registers values Friday. Following are configuration setting inside C code:
        

          

        • PWRMODE = high resolution,
          • 

        • Clock prescaler = 1 (DCLK_DIV),
          • 

        • ODR = 5kHz,
          • 

        • Use external reference.
          • 

        

        

        Note: if I don't try to command START pin (no synchronization), DRDY signal comes every 200µs.
        

        

        Thanks,
        

        Martial
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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                on Apr 18, 2025 12:02 PM
            
            
												
						in reply to Martial73
					
										
			            		
          
		
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          Hello,
          

          

          Here you can find all registers value : 
          

          



          
    
          
        Fullscreen
        AD7779_register.txt
        Download
    
          
    
          [0]	  unsigned int	0x0000 (Hex)	
[1]	  unsigned int	0x0000 (Hex)	
[2]	  unsigned int	0x0000 (Hex)	
[3]	  unsigned int	0x0000 (Hex)	
[4]	  unsigned int	0x0000 (Hex)	
[5]	  unsigned int	0x0000 (Hex)	
[6]	  unsigned int	0x0000 (Hex)	
[7]	  unsigned int	0x0000 (Hex)	
[8]	  unsigned int	0x00FC (Hex)	
[9]	  unsigned int	0x0000 (Hex)	
[10]	unsigned int	0x0000 (Hex)
[11]	unsigned int	0x0000 (Hex)
[12]	unsigned int	0x0000 (Hex)
[13]	unsigned int	0x0000 (Hex)
[14]	unsigned int	0x0000 (Hex)
[15]	unsigned int	0x0000 (Hex)
[16]	unsigned int	0x0000 (Hex)
[17]	unsigned int	0x0064 (Hex)
[18]	unsigned int	0x0009 (Hex)
[19]	unsigned int	0x0080 (Hex)
[20]	unsigned int	0x0020 (Hex)
[21]	unsigned int	0x0000 (Hex)
[22]	unsigned int	0x0000 (Hex)
[23]	unsigned int	0x0000 (Hex)
[24]	unsigned int	0x0038 (Hex)
[25]	unsigned int	0x0038 (Hex)
[26]	unsigned int	0x00C0 (Hex)
[27]	unsigned int	0x0000 (Hex)
[28]	unsigned int	0x0000 (Hex)
[29]	unsigned int	0x0000 (Hex)
[30]	unsigned int	0x0000 (Hex)
[31]	unsigned int	0x0055 (Hex)
[32]	unsigned int	0x0058 (Hex)
[33]	unsigned int	0x00E5 (Hex)
[34]	unsigned int	0x0000 (Hex)
[35]	unsigned int	0x0000 (Hex)
[36]	unsigned int	0x0000 (Hex)
[37]	unsigned int	0x0055 (Hex)
[38]	unsigned int	0x0050 (Hex)
[39]	unsigned int	0x00C5 (Hex)
[40]	unsigned int	0x0000 (Hex)
[41]	unsigned int	0x0000 (Hex)
[42]	unsigned int	0x0000 (Hex)
[43]	unsigned int	0x0055 (Hex)
[44]	unsigned int	0x0057 (Hex)
[45]	unsigned int	0x0045 (Hex)
[46]	unsigned int	0x0000 (Hex)
[47]	unsigned int	0x0000 (Hex)
[48]	unsigned int	0x0000 (Hex)
[49]	unsigned int	0x0055 (Hex)
[50]	unsigned int	0x0053 (Hex)
[51]	unsigned int	0x00C5 (Hex)
[52]	unsigned int	0x0000 (Hex)
[53]	unsigned int	0x0000 (Hex)
[54]	unsigned int	0x0000 (Hex)
[55]	unsigned int	0x0055 (Hex)
[56]	unsigned int	0x0056 (Hex)
[57]	unsigned int	0x0095 (Hex)
[58]	unsigned int	0x0000 (Hex)
[59]	unsigned int	0x0000 (Hex)
[60]	unsigned int	0x0000 (Hex)
[61]	unsigned int	0x0055 (Hex)
[62]	unsigned int	0x0057 (Hex)
[63]	unsigned int	0x00A5 (Hex)
[64]	unsigned int	0x0000 (Hex)
[65]	unsigned int	0x0000 (Hex)
[66]	unsigned int	0x0000 (Hex)
[67]	unsigned int	0x0055 (Hex)
[68]	unsigned int	0x0055 (Hex)
[69]	unsigned int	0x0055 (Hex)
[70]	unsigned int	0x0000 (Hex)
[71]	unsigned int	0x0000 (Hex)
[72]	unsigned int	0x0000 (Hex)
[73]	unsigned int	0x0055 (Hex)
[74]	unsigned int	0x0057 (Hex)
[75]	unsigned int	0x0095 (Hex)
[76]	unsigned int	0x0000 (Hex)
[77]	unsigned int	0x0000 (Hex)
[78]	unsigned int	0x0000 (Hex)
[79]	unsigned int	0x0000 (Hex)
[80]	unsigned int	0x0000 (Hex)
[81]	unsigned int	0x0000 (Hex)
[82]	unsigned int	0x0000 (Hex)
[83]	unsigned int	0x0000 (Hex)
[84]	unsigned int	0x0000 (Hex)
[85]	unsigned int	0x0000 (Hex)
[86]	unsigned int	0x0000 (Hex)
[87]	unsigned int	0x0000 (Hex)
[88]	unsigned int	0x00FF (Hex)
[89]	unsigned int	0x0000 (Hex)
[90]	unsigned int	0x003F (Hex)
[91]	unsigned int	0x0000 (Hex)
[92]	unsigned int	0x003C (Hex)
[93]	unsigned int	0x0000 (Hex)
[94]	unsigned int	0x0000 (Hex)
[95]	unsigned int	0x0010 (Hex)
[96]	unsigned int	0x0001 (Hex)
[97]	unsigned int	0x0099 (Hex)
[98]	unsigned int	0x0000 (Hex)
[99]	unsigned int	0x0000 (Hex)
[100]	unsigned int	0x0000 (Hex)

          

          


          

          Use SPI_SYNC bit have the same effect describe before : a pulse is generated on SYNC_IN signal and DRDY pulses never appear.
          

          

          On the paper, is it possible to do what I have describe before (on figure) ?
          

          

          Best regards,
          

          Martial
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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                on Apr 28, 2025 8:58 AM
            
            
												
						in reply to Martial73
					
										
			            		
            
		
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            Hello Janine,
            

            Do you working on my issue ? If yes, could you give me information ?
            

            Best regards,
            

            Martial
            
			
            

		
			
	      

		
		
	
            
	
            
		
            
			
		
            
	
            
	
            
		
						
						
				
						
				
				
		
		
            
			
		
            
	
            

            

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            •  Analog Employees  
            
            
						
                            
            
            				
            
                on May 15, 2025 2:46 AM
            
            
												
						in reply to Martial73
					
										
			            		
            
		
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            Hi  ,
            

            Apologies for the delay. The schematic and registers look correct to me except for the bit 4 of register 0x5F. Can you please issue a reset pulse after power-up and check again?
            

            I would like to clarify, there is DRDY pulse after power-up? But DRDY pulse is gone after issuing a sync pulse using SPI_SYNC register, SYNC_IN pin, or START pin?
            

            Martial73 said:
            I set my ODR at 5kHz to have a DRDY pulse each 200µs. I'm not sure to understand the difference between samples available every 250µs and ODR = 4kHz. Could you explain to me ?
            

            From the figure, there is 250uS between DRDY pulses, and I had assumed you wanted to set ODR at 4kHz.
            

            Thanks,
            Janine
            
			
            

		
			
	      

		
		
	
            
	
            
		
            
			
		
            
	
            
	
            
		
						
						
						
						
				
				
		
		
            
			
		
            
	
            

            

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                on Aug 29, 2025 5:44 AM
            
            
												
						in reply to JEstayo
					
										
			            		
              
		
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              Hello,
              

              Sorry I didn’t see your last response. I don’t understand why you say the register is not set to the correct value, since it is at 0x10, which indicates no error and a complete initialization.
              

               
              

               
              

              Thank you for your feedback,
              

              Martial
              
			
              

		
			
	      

		
		
	
              
	
              
		
              
			
		
              
	
              
	
              
		
						
						
				
						
				
				
		
		
              
			
		
              
	
              

              

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