AD4134 SPI Data Read Issue & Minimum SPI Mode Clarification

Controller: STM32H7A3ZIT6Q
ADC: AD4134
Communication: SPI (4-wire mode)
Data Size: 8-bit
MSB First
SPI Mode: CPOL = 0, CPHA = 0 (Mode 0)
Frequency: 4 MHz

PIN/SPI - HIGH

RESET -  HIGH

1.Issue: Unexpected Data on SDO When Power is Off

• Hardware is configured according to Table 22 in the AD4134 datasheet.

• Clock Type: CMOS.

• Problem:

  • Observed unexpected data on the SDO line using a CRO when the unit is powered off.

  • However, reading Vendor ID & Scratch Pad ,INTERFACE_CONFIG_A  max all registers works correctly.

  • Verified all power supplies, and they are functioning properly.

  • Still unable to identify the root cause of this issue.

 Question:

• What could be causing data to appear on SDO while the unit is powered off?

2. Minimum SPI Mode – ADC Data Read Process

• I want to confirm the correct procedure for reading ADC data in Minimum SPI Mode.

• Based on my understanding, after toggling the ODR pin, we should read 24-bit ADC data, and this process repeats for every sample.

 Question:

• Is this the correct method for reading ADC data in Minimum SPI Mode?

3.ADC Data Frame Format – Multi-Channel Output on SDO

• When reading 4-channel ADC data on the SDO pin, how is the data structured?

  • Is it interleaved (mixing samples from different channels sequentially)?

  • Or is it channel-wise, where all samples from one channel are read first before moving to the next?

 Question:

• What is the correct frame format when reading 4-channel data on SDO?

4.

Question: SPI Locking & Unlocking Pattern for Minimum I/O Mode

• What is the SPI locking/unlocking sequence for AD4134 in Minimum I/O Mode?

• Is there any reference or documentation explaining how to implement this correctly?