AD4134 SPI Data Read Issue & Minimum SPI Mode Clarification

Hi Bitsams ,

Please refer to the initial answers below. I will confirm other details and get back.

1. Is there connection between AD4134 and STM32 when you measured it? I will look into this more and get back.
2. Yes. With sufficient SCLK, you should be able to read data over SDO, configure the ADC as page 69 and check. From what I know, SPI of STM does not support the this data format over SPI.
3. The data of the 4 channel will be interleaved like the figure below

4. I will look into this further and get back.

Thanks,
Janine

Hi Bitsams ,

On your question about SPI locking & unlocking, there is only that section on the datasheet.

Writing 24 consecutive 1s will lock SPI (read or write commands will be ignored). To unlock, write 23 1s and one 0.

Thanks,
Janine

HI jestayo

thanks for response .

due to pull resistor on cs , i cant access registers ,but its working and capturing data some more question i have please help me. .

Currently accessing AD4134 using two SPI interfaces:

• One SPI is connected to SDI, SDO, SCLK, and CS.

• Another SPI is connected to DOUT1(SDO) and DCLK.(SCLK)

AD4134 is in ASRC slave mode with the following configuration:

• ODR and DCLK are configured as inputs.

• Gated DCLK is used.

• Clock type: CMOS.

• XCLKOUT_EN is enabled, and I observed 48MHz at both the input and output, which is working correctly.

• Operating ODR as gpio output.maintaing ODR high time as per figure 2.

Issues faced:

1. Unable to access all registers. Some write operations (e.g., power-down register) are not successful. How can I ensure all registers are accessible?

2. Chip error observed. The DIG_FILTER_OFUF register shows 0xF. What could be the reason for this error?

3. Issue with data capture speed:

   • Set DIGITAL_INTERFACE_CONFIG to configured FORMAT = 0, meaning data from all four ADC channels should be output on DOUT0.

   •  Set frame 24-bit data only.

   • At SPI clock = 3MHz, data from all four channels is captured correctly.

   • At SPI clock > 6MHz, only two channels work correctly 48clocks , while trying to capture 4 channels generating 96 clocks getting constant data.

   • Why does increasing the SPI clock affect data capture for all channels?

4. Channel selection clarification:

   • Based on my understanding, if I want data from only channel 1 and channel 4, I should power down channel 2 and channel 3. Is this correct?

5. How can I achieve high-speed data acquisition for all channels?