I am creating a project with an AD7124-8 PMDZ eval board with an STM32H755ZI nucleo board.

Communicating through :
SPI Mode - 3 ( CPOL - 1, CPHA - 1 ),
MSB first,
8 bit data length,
No CRC.
I have Hardware NSS output enabled.

The No-Os drivers do not work with the H7 line of STM32 processors, hence I set out to create my own small driver for this powerful ADC. The following are the register reading and writing functions that I wrote.

void AD7124_WriteRegister(uint8_t reg_addr, uint8_t *data, uint8_t length) {

uint8_t command = 0x00 | (reg_addr & 0x3F);

uint8_t txBuffer[length + 1];

txBuffer[0] = command;

for (uint8_t i = 0; i < length; i++) {

txBuffer[i + 1] = data[i];

}

HAL_SPI_Transmit(&hspi1, txBuffer, length + 1, 100);

}

void AD7124_ReadRegister(uint8_t reg_addr, uint8_t *data, uint8_t length) {

uint8_t command = 0x40 | (reg_addr & 0x3F);1

uint8_t txBuffer[length + 1];

uint8_t rxBuffer[length + 1];

txBuffer[0] = command;

memset(&txBuffer[1], 0x00, length);

memset(rxBuffer, 0x00, length + 1);

HAL_SPI_TransmitReceive(&hspi1, txBuffer, rxBuffer, length + 1, 100);

for (uint8_t i = 0; i < length; i++) {

data[i] = rxBuffer[i + 1];

}

}

Writing to registers snippet:

AD7124_Reset();

HAL_Delay(1);

uint8_t adc_ctrl[2] = {0x02, 0xA3};

AD7124_WriteRegister(0x01, adc_ctrl, 2);

HAL_Delay(1);

uint8_t setup_config[2] = {0x08, 0x10};

AD7124_WriteRegister(0x19, setup_config, 2);

HAL_Delay(1);

uint8_t ch0_enable[2] = {0x80, 0x01};

AD7124_WriteRegister(0x09, ch0_enable, 2);

HAL_Delay(1);

uint8_t ch_enable[2] = {0x80, 0x43};

AD7124_WriteRegister(0x0A, ch_enable, 2);

HAL_Delay(1);

reading from registers snippet:

uint8_t error_read[3] = {0};

AD7124_ReadRegister(0x06, error_read, 3);

snprintf((char*)buff, sizeof(buff), "error (Readback): 0x%02X%02X%02X\n", error_read[0], error_read[1], error_read[2]);

CDC_Transmit_FS(buff, strlen((char const *)buff));

HAL_Delay(1);

uint8_t status_read[1] = {0};

AD7124_ReadRegister(0x00, status_read, 2);

snprintf((char*)buff, sizeof(buff), "status (Readback): 0x%02X\n\n\n", status_read[0]);

CDC_Transmit_FS(buff, strlen((char const *)buff));

THE PROBLEM:

Reading the ID register gives back 0x14, which does not match with the datasheet default value for this register but, this FAQ reflects that the standard part has the ID of 0x14.

Now writing to and reading from the registers gives equal results. eg - writing 0x8043 to the channel 1 register( 0x0A ), and then reading it back gives me 0x8043.

However enabled channels should be reflected in the status register which gives me 0x80, instead of the expected 0x81.

Here is the datasheet link.

I have been stuck on this for a while now. any help would be appreciated.