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MAX1220/MAX1258 miso delayed one clock cycle, how to convert MISO data from SPI bus?

Category: Datasheet/Specs
Product Number: MAX1220
Hello, I don't understand the following (mentionned in the MAX1258 evaluation board):
mstr-in slve-out data from MAX1258 is delayed one clock cycle.
** When instructed to transfer n bytes, the hardware must generate
** n * 8 clock pulses. However, the first bit of miso_buf[] must be sampled
** concurrent with the SECOND bit of mosi[].
** The final bit of miso_buf[] does not get a clock pulse, instead the
** final state of the MAX1258 DOUT pin is sampled prior to negating CS.
 
Could someone please clarify more ?
Below is a screen shot of my spi bus where I send a conversion byte and then receive on 16 clock cycles the answer from the adc :
 
I'm in 10 clock mode and the ADC is internaly referenced (Vref=4.096V and since the ADC is 12 bits so 2^12=4096 so each bit corresponds to 1mV), so according to the datasheet (see below), the voltage of 3.76V I send to the adc Analog Pin 0 should be represented in tthe two receiving 8 clock cycles on the right.
The logic analyzer reads 0x07 and 0xFF wich represents 2047 mV and not 3760 mV. I reach aproximatly voltage when i shift the 0x07 by one bit to the left wich gives 0xE and 0xEFF is 3839 so I'm close to 3760mV.
But I'm not sure what i do above is correct and corresponds to the delayed by one clock cycle thing discribed in the begining of my issue.
Can someone please clarify and apply the correct transformation on the 0x07FF example to have the coorect reading ?
Thank you !
 

Edit Notes

added LMXMprodsupport in tag
[edited by: RAdante at 11:27 AM (GMT -4) on 9 Mar 2025]