mstr-in slve-out data from MAX1258 is delayed one clock cycle.
** When instructed to transfer n bytes, the hardware must generate
** n * 8 clock pulses. However, the first bit of miso_buf[] must be sampled
** concurrent with the SECOND bit of mosi[].
** The final bit of miso_buf[] does not get a clock pulse, instead the
** final state of the MAX1258 DOUT pin is sampled prior to negating CS.

But I'm not sure what i do above is correct and corresponds to the delayed by one clock cycle thing discribed in the begining of my issue.
Can someone please clarify and apply the correct transformation on the 0x07FF example to have the coorect reading ?
Thank you !

Edit Notes
added LMXMprodsupport in tag[edited by: RAdante at 11:27 AM (GMT -4) on 9 Mar 2025]