Configuraton Register Readback for AD7949 IC

Question

Hello, 
 I want to do a readback to the register inside the AD7949 integrated circuit. When I do a readback to the configuration register, I can read it not at the first time but at the 3rd time, I have the same problem every time I want to read it back. I am trying to do these operations using FPGA, with SPI protocol, SPI frequency is 6.25 MHz. Can you help me why I read it at the 3rd time? Is this how the ADC works? I uploaded the ILA PICTURE with the signals related to the issue below. First I sent two dummy conversions, then I sent the 28'hFF38000 data, after two data transactions it returned the data I sent. Is this how the ADC works or is this a mistake I made?

zsa · Accepted Answer

Expected data is supposed to be read back at the 3rd iteration. 
 
 Similar to the ADC data readback, the CFG readback also has a 2-cycle delay. I think the datasheet wording might be a bit confusing:

Here, it says one deep delay, but that deep delay actually means when you write to the CFG register, it will get updated at the end of the current conversion. But then you need another conversion to display new ADC data along with the CFG register value.

When you write to CFG in the 'n' cycle, the register gets updated at the end of 'n'. Then, there is an acquisition and conversion in the 'n+1' cycle, and then you read back at 'n+2'.)

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Configuraton Register Readback for AD7949 IC