AD7616
Production
The AD7616 is a 16-bit, DAS that supports dual simultaneous sampling of 16 channels. The AD7616 operates from a single 5 V supply and can accommodate ...
Datasheet
AD7616 on Analog.com
Hi,
when reading 16 channel conversion results in burst mode, we will pulse CS high between every channel conversion result.
If SDI is kept low during the 16 channel conversion results clocked out period, we can get the correct result.
If SDI is kept high during the 16 channel conversion results clocked out period, we will get the wrong result and the conversion result read out is close to 0(no matter what's the voltage value applied at the ADC input).
And I find on the datasheet it's said:
If the status register is appended to the conversion results or operating in sequencer burst mode where multiples of 16 SCLK transfers access data from the AD7616, hold CS low to frame the entire data.
My question is:
If we keep CS low during the whole 16 channel conversion result clocked out period, do we still need to keep SDI low to get the correct result?
Why do we need to keep CS low during the whole 16 channel conversion result clocked out period, can we still pulse CS high between each channel conversion result clocked out period?
Hi, howardaaa .
Your observation is on track. Relating your question to figures 2 and 6. The enclosed sections are the conversion phases across all interfaces, serial or parallel mode. And you should wait for the tCONV to finish, wait to be in the acquisition phase, before setting up your SDI or to be removed in three-state/tri-state. Note: Refer to the tSCLK_SETUP timing spec.
Why do we need to keep CS low during the whole 16 channel conversion result clocked out period, can we still pulse CS high between each channel conversion result clocked out period?
The CS falling edge takes the data output lines, SDOA and SDOB, out of three-state and clocks out the MSB of the conversion result. After the 16 cycles, CS must be toggled high. And the sequence goes on. Lastly, to achieve the maximum throughput, it is required to use 2-wire mode.
Warm regards,
Jo
Hi, howardaaa .
Generally speaking, if we put the SDI low during the clocking out of data, I would say that it is the optimize configuration of an ADC. Since you are telling the ADC that you don't have any more configuration, nor any changes within your SDI line. Also, some ADC's default register for the conversion result is 0x0000. Thus, it is safe to make SDI low.
Why do we need to keep CS low during the whole 16 channel conversion result clocked out period, can we still pulse CS high between each channel conversion result clocked out period?
Relating this to figure 58. You have the option to make it low all throughout. Or toggle it high in between conversions of channel every after 16 cycles.
Regards,
Jo
