Hi,
I am analyzing the AD7367 datasheet (Rev. D) and I am confused on the "Serial Interface" section (page 22-23) for SPI communication and I' ve asked to myself that "it is realy compatible with SPI or am I missing something or I don't know something?". The reasons for that question are in the below;
1- In the figure 26, I found out the SPI CPOL could be "0" or "1" but I see the SPI clock polarity must be "1" in the figure 28. Which one is true or CPOL must be "1" when reading both data of ADCs from a same pin, and CPOL could be "0" or "1" when reading data from seperate pins (DOUTA and DOUTB). ??
2- In the text below of the "Serial Interface" section, it says that
"The data stream consists of 14 bits of data for the AD7367, MSB first. The first bit of the conversion result is valid on the first SCLK falling edge after the CS falling edge. The subsequent 11/13 bits of data for the AD7366/AD7367, respectively, are clocked out on the falling edge of the SCLK signal. A minimum of 14 clock pulses must be provided to the AD7367 to access the conversion result."
So, I infer in general data is shifted out on the falling edge and so data can be sampled on the rising edge.So I figure out also from the timing diagrams and SPI Mode 0 and Mode 3 (both modes sample data on the rising edge of clock and shifted data on the falling edge of clock) can be used to read data from that IC. But what about first bit?? Why it is ready after the CS is activated? Is not It must be shifted out after first falling edge of SCK? I' ve searched on the internet and according to the experinces with other SPI ICs (include Analog Device) until now is like same according to the referred. Even in the article of Analog Device about SPI (https://www.analog.com/en/resources/analog-dialogue/articles/introduction-to-spi-interface.html). See the below figures for SPI mode 0 and 3. Also in these figures MISO line should be high-z until first sample edge of SCK. Why the AD7367 immediately prepare MSb (most significant bit, 13. bit) after the CS is low and change the right away on the first falling edge of SCK (goes next bit, 12. bit). I can not read first bit (MSB) of data on the first sample edge. Why was it done like this, is there a reason? Is it compatible with SPI?
---------------------------- Datasheet page 22-23 ----------------------------
