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Can I use the ADAQ23878 with a 1.8V LVDS interface?

Category: Datasheet/Specs
Product Number: ADAQ23878

Can I use the ADAQ23878 with a 1.8V LVDS interface?

The ADAQ23878 LVDS interface power supply is VIO (2.5V), but can I use it with a 1.8V LVDS (FPGA)?

Once communication begins, the amplitude voltage is maintained at 350mV centered around 1.25V, so there is no problem if the receiving FPGA is 1.8V, but
before communication, the output will be H (2.5V).

Q1: Is it a specification that the LVDS signal lines "CNV+/-", "CLK+/-", "DCO+/-", and "DA+/-" are pulled by the 2.5V VIO before LVDS communication is established?

Q2: If it is a specification, is there a way to prevent it from becoming 2.5V (GND level or high impedance state)?

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