ad7768-1 linux

Hi,

We will look into this and get back to you.

Thanks,
Janine

Thanks,I'll be looking forward to your future reply!

Hi mypustc  ,

Could you share details about your current hardware setup and the controller you are using to interface with the CN0535 board? If possible, photos would also be very helpful for us to get a better understanding.

Thanks,
Andy

I'm using cn0535(incorporating ad7768-1) connecting with firefly itx-3588j(using rockchip rk3588, arm based embedded system),the system connection and basic function is in going well,but if i use the system to capture the out-connected sinusoid signal,the data is like this:

the shape is ok,but the cycle is distorted.

so i captured the trigger and cs signal with oscilloscope:

the cs signal is obviously seen not properly replied

// SPDX-License-Identifier: GPL-2.0 /* * Analog Devices AD7768-1 SPI ADC driver * * Copyright 2017 Analog Devices Inc. */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/err.h> #include <linux/gpio/consumer.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/regulator/consumer.h> #include <linux/sysfs.h> #include <linux/spi/spi.h> #include <linux/iio/buffer.h> #include <linux/iio/iio.h> #include <linux/iio/sysfs.h> #include <linux/iio/trigger.h> #include <linux/iio/triggered_buffer.h> #include <linux/iio/trigger_consumer.h> #include <linux/gpio.h> #include <linux/of_gpio.h> #define SET_SYNC_IN /* AD7768 registers definition */ #define AD7768_REG_CHIP_TYPE 0x3 #define AD7768_REG_PROD_ID_L 0x4 #define AD7768_REG_PROD_ID_H 0x5 #define AD7768_REG_CHIP_GRADE 0x6 #define AD7768_REG_SCRATCH_PAD 0x0A #define AD7768_REG_VENDOR_L 0x0C #define AD7768_REG_VENDOR_H 0x0D #define AD7768_REG_INTERFACE_FORMAT 0x14 #define AD7768_REG_POWER_CLOCK 0x15 #define AD7768_REG_ANALOG 0x16 #define AD7768_REG_ANALOG2 0x17 #define AD7768_REG_CONVERSION 0x18 #define AD7768_REG_DIGITAL_FILTER 0x19 #define AD7768_REG_SINC3_DEC_RATE_MSB 0x1A #define AD7768_REG_SINC3_DEC_RATE_LSB 0x1B #define AD7768_REG_DUTY_CYCLE_RATIO 0x1C #define AD7768_REG_SYNC_RESET 0x1D #define AD7768_REG_GPIO_CONTROL 0x1E #define AD7768_REG_GPIO_WRITE 0x1F #define AD7768_REG_GPIO_READ 0x20 #define AD7768_REG_OFFSET_HI 0x21 #define AD7768_REG_OFFSET_MID 0x22 #define AD7768_REG_OFFSET_LO 0x23 #define AD7768_REG_GAIN_HI 0x24 #define AD7768_REG_GAIN_MID 0x25 #define AD7768_REG_GAIN_LO 0x26 #define AD7768_REG_SPI_DIAG_ENABLE 0x28 #define AD7768_REG_ADC_DIAG_ENABLE 0x29 #define AD7768_REG_DIG_DIAG_ENABLE 0x2A #define AD7768_REG_ADC_DATA 0x2C #define AD7768_REG_MASTER_STATUS 0x2D #define AD7768_REG_SPI_DIAG_STATUS 0x2E #define AD7768_REG_ADC_DIAG_STATUS 0x2F #define AD7768_REG_DIG_DIAG_STATUS 0x30 #define AD7768_REG_MCLK_COUNTER 0x31 /* AD7768_REG_POWER_CLOCK */ #define AD7768_PWR_MCLK_DIV_MSK GENMASK(5, 4) #define AD7768_PWR_MCLK_DIV(x) FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x) #define AD7768_PWR_PWRMODE_MSK GENMASK(1, 0) #define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x) /* AD7768_REG_DIGITAL_FILTER */ #define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4) #define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x) #define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0) #define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x) /* AD7768_REG_CONVERSION */ #define AD7768_CONV_MODE_MSK GENMASK(2, 0) #define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x) #define AD7768_RD_FLAG_MSK(x) (BIT(6) | ((x) & 0x3F)) #define AD7768_WR_FLAG_MSK(x) ((x) & 0x3F) enum ad7768_conv_mode { AD7768_CONTINUOUS, AD7768_ONE_SHOT, AD7768_SINGLE, AD7768_PERIODIC, AD7768_STANDBY }; enum ad7768_pwrmode { AD7768_ECO_MODE = 0, AD7768_MED_MODE = 2, AD7768_FAST_MODE = 3 }; enum ad7768_mclk_div { AD7768_MCLK_DIV_16, AD7768_MCLK_DIV_8, AD7768_MCLK_DIV_4, AD7768_MCLK_DIV_2 }; enum ad7768_dec_rate { AD7768_DEC_RATE_32 = 0, AD7768_DEC_RATE_64 = 1, AD7768_DEC_RATE_128 = 2, AD7768_DEC_RATE_256 = 3, AD7768_DEC_RATE_512 = 4, AD7768_DEC_RATE_1024 = 5, AD7768_DEC_RATE_8 = 9, AD7768_DEC_RATE_16 = 10 }; struct ad7768_clk_configuration { enum ad7768_mclk_div mclk_div; enum ad7768_dec_rate dec_rate; unsigned int clk_div; enum ad7768_pwrmode pwrmode; }; static const struct ad7768_clk_configuration ad7768_clk_config[] = { { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE }, { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE }, { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE }, { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE }, { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE }, { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE }, { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE }, { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE }, { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE }, { AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE }, { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE }, }; static const struct iio_chan_spec ad7768_channels[] = { { .type = IIO_VOLTAGE, .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), .indexed = 1, .channel = 0, .scan_index = 0, .scan_type = { .sign = 'u', .realbits = 24, .storagebits = 32, .shift = 8, .endianness = IIO_BE, }, }, }; struct ad7768_state { struct spi_device *spi; struct regulator *vref; struct mutex lock; struct clk *mclk; unsigned int mclk_freq; unsigned int samp_freq; struct completion completion; struct iio_trigger *trig; struct gpio_desc *gpio_sync_in; /* * DMA (thus cache coherency maintenance) requires the * transfer buffers to live in their own cache lines. */ union { struct { __be32 chan; s64 timestamp; } scan; __be32 d32; u8 d8[2]; } data ____cacheline_aligned; }; static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr, unsigned int len) { unsigned int shift; int ret; shift = 32 - (8 * len); st->data.d8[0] = AD7768_RD_FLAG_MSK(addr); ret = spi_write_then_read(st->spi, st->data.d8, 1, &st->data.d32, len); if (ret < 0) return ret; return (be32_to_cpu(st->data.d32) >> shift); } static int ad7768_spi_reg_write(struct ad7768_state *st, unsigned int addr, unsigned int val) { st->data.d8[0] = AD7768_WR_FLAG_MSK(addr); st->data.d8[1] = val & 0xFF; return spi_write(st->spi, st->data.d8, 2); } static int ad7768_set_mode(struct ad7768_state *st, enum ad7768_conv_mode mode) { int regval; int ret; regval = ad7768_spi_reg_read(st, AD7768_REG_CONVERSION, 1); if (regval < 0) return regval; regval &= ~AD7768_CONV_MODE_MSK; regval |= AD7768_CONV_MODE(mode); ret= ad7768_spi_reg_write(st, AD7768_REG_CONVERSION, regval); if (ret < 0) return ret; #ifdef SET_SYNC_IN ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET,0); if (ret < 0) { printk(KERN_ERR "hank spi %s %d AD7768_REG_SYNC_RESET failed \n",__FUNCTION__,__LINE__); return ret; } #endif return ret; } static int ad7768_scan_direct(struct iio_dev *indio_dev) { struct ad7768_state *st = iio_priv(indio_dev); int readval, ret; reinit_completion(&st->completion); ret = ad7768_set_mode(st, AD7768_ONE_SHOT); if (ret < 0) return ret; ret = wait_for_completion_timeout(&st->completion, msecs_to_jiffies(1000)); if (!ret) return -ETIMEDOUT; readval = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3); if (readval < 0) return readval; /* * Any SPI configuration of the AD7768-1 can only be * performed in continuous conversion mode. */ ret = ad7768_set_mode(st, AD7768_CONTINUOUS); if (ret < 0) return ret; return readval; } static int ad7768_reg_access(struct iio_dev *indio_dev, unsigned int reg, unsigned int writeval, unsigned int *readval) { struct ad7768_state *st = iio_priv(indio_dev); int ret; int i; mutex_lock(&st->lock); if (readval) { if(reg == 256) //hank add : dump all register 0~0x34 { printk(KERN_ERR "AD7768-1 all register dump:"); for(i=0;i<0x35;i++) { if(i==0x2c){ ret = ad7768_spi_reg_read(st, i, 3); printk(KERN_ERR "reg 0x%x=%d\n",i,ret); } else{ ret = ad7768_spi_reg_read(st, i, 1); printk(KERN_ERR "reg 0x%x=0x%x\n",i,ret); } if (ret < 0) goto err_unlock; } *readval = i; ret = 0; } else { ret = ad7768_spi_reg_read(st, reg, 1); if (ret < 0) goto err_unlock; *readval = ret; ret = 0; } } else { ret = ad7768_spi_reg_write(st, reg, writeval); } err_unlock: mutex_unlock(&st->lock); return ret; } static int ad7768_set_dig_fil(struct ad7768_state *st, enum ad7768_dec_rate dec_rate) { unsigned int mode; int ret; if (dec_rate == AD7768_DEC_RATE_8 || dec_rate == AD7768_DEC_RATE_16) mode = AD7768_DIG_FIL_FIL(dec_rate); else mode = AD7768_DIG_FIL_DEC_RATE(dec_rate); ret = ad7768_spi_reg_write(st, AD7768_REG_DIGITAL_FILTER, mode); if (ret < 0) return ret; /* A sync-in pulse is required every time the filter dec rate changes */ //gpiod_set_value(st->gpio_sync_in, 1); //gpiod_set_value(st->gpio_sync_in, 0); //gpiod_set_value(st->gpio_sync_in, 0); //gpiod_set_value(st->gpio_sync_in, 1); #ifdef SET_SYNC_IN ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET,0); if (ret < 0) { printk(KERN_ERR "hank spi %s %d AD7768_REG_SYNC_RESET failed \n",__FUNCTION__,__LINE__); return ret; } #endif return ret; } static int ad7768_set_freq(struct ad7768_state *st, unsigned int freq) { unsigned int diff_new, diff_old, pwr_mode, i, idx; int res, ret; diff_old = U32_MAX; idx = 0; res = DIV_ROUND_CLOSEST(st->mclk_freq, freq); /* Find the closest match for the desired sampling frequency */ for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) { diff_new = abs(res - ad7768_clk_config[i].clk_div); if (diff_new < diff_old) { diff_old = diff_new; idx = i; } } /* * Set both the mclk_div and pwrmode with a single write to the * POWER_CLOCK register */ pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) | AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode); ret = ad7768_spi_reg_write(st, AD7768_REG_POWER_CLOCK, pwr_mode); if (ret < 0) return ret; ret = ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate); if (ret < 0) return ret; st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq, ad7768_clk_config[idx].clk_div); return 0; } static ssize_t ad7768_sampling_freq_avail(struct device *dev, struct device_attribute *attr, char *buf) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct ad7768_state *st = iio_priv(indio_dev); unsigned int freq; int i, len = 0; for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) { freq = DIV_ROUND_CLOSEST(st->mclk_freq, ad7768_clk_config[i].clk_div); len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", freq); } buf[len - 1] = '\n'; return len; } static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(ad7768_sampling_freq_avail); static int ad7768_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long info) { struct ad7768_state *st = iio_priv(indio_dev); int scale_uv, ret; switch (info) { case IIO_CHAN_INFO_RAW: // myp added below: buffer and read_raw confict if (iio_buffer_enabled(indio_dev)) return -EBUSY; // myp added above: no simultaneous ret = iio_device_claim_direct_mode(indio_dev); if (ret) return ret; ret = ad7768_scan_direct(indio_dev); if (ret >= 0) { *val = ret; } iio_device_release_direct_mode(indio_dev); if (ret < 0) return ret; return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: //scale_uv = regulator_get_voltage(st->vref); scale_uv=4096000; //hank add if (scale_uv < 0) return scale_uv; *val = (scale_uv * 2) / 1000; *val2 = chan->scan_type.realbits; return IIO_VAL_FRACTIONAL_LOG2; case IIO_CHAN_INFO_SAMP_FREQ: *val = st->samp_freq; return IIO_VAL_INT; } return -EINVAL; } static int ad7768_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long info) { struct ad7768_state *st = iio_priv(indio_dev); switch (info) { case IIO_CHAN_INFO_SAMP_FREQ: return ad7768_set_freq(st, val); default: return -EINVAL; } } static struct attribute *ad7768_attributes[] = { &iio_dev_attr_sampling_frequency_available.dev_attr.attr, NULL }; static const struct attribute_group ad7768_group = { .attrs = ad7768_attributes, }; static const struct iio_info ad7768_info = { .attrs = &ad7768_group, .read_raw = &ad7768_read_raw, .write_raw = &ad7768_write_raw, .debugfs_reg_access = &ad7768_reg_access, }; static int ad7768_setup(struct ad7768_state *st) { int ret; /* * Two writes to the SPI_RESET[1:0] bits are required to initiate * a software reset. The bits must first be set to 11, and then * to 10. When the sequence is detected, the reset occurs. * See the datasheet, page 70. */ ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x3); printk(KERN_ERR "hank spi test %s %d ret=%d\n",__FUNCTION__,__LINE__,ret); if (ret) return ret; ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x2); printk(KERN_ERR "hank spi test %s %d ret=%d\n",__FUNCTION__,__LINE__,ret); if (ret) return ret; st->gpio_sync_in = devm_gpiod_get(&st->spi->dev, "adi,sync-in", GPIOD_OUT_LOW); //printk(KERN_ERR "hank spi test %s %d \n",__FUNCTION__,__LINE__); if (IS_ERR(st->gpio_sync_in)) return PTR_ERR(st->gpio_sync_in); /* Set the default sampling frequency to 32000 kSPS */ printk(KERN_ERR "hank spi test %s %d \n",__FUNCTION__,__LINE__); return ad7768_set_freq(st, st->samp_freq); } static irqreturn_t ad7768_trigger_handler(int irq, void *p) { struct iio_poll_func *pf = p; struct iio_dev *indio_dev = pf->indio_dev; struct ad7768_state *st = iio_priv(indio_dev); int ret; //static unsigned int count=1; //gpiod_set_value(st->gpio_sync_in, 1); //gpiod_set_value(st->gpio_sync_in, 0); //st->spi->controller->set_cs(st->spi, true); // myp added //printk(KERN_ERR "hank spi test %s %d \n",__FUNCTION__,__LINE__); mutex_lock(&st->lock); //ret = spi_read(st->spi, &st->data.scan.chan, 3); ret = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3); st->data.scan.chan=ret; //st->data.scan.chan=count; //count++; if (ret < 0) goto err_unlock; //if(count==2) //printk(KERN_ERR "hank spi test %s %d scan_timestamp=%d scan_bytes=%d size=%d timestamp=%lld\n",__FUNCTION__,__LINE__,(int)indio_dev->scan_timestamp,(int)indio_dev->scan_bytes,(int)sizeof(int64_t),iio_get_time_ns(indio_dev) ); iio_push_to_buffers_with_timestamp(indio_dev, &st->data.scan, iio_get_time_ns(indio_dev)); err_unlock: iio_trigger_notify_done(indio_dev->trig); mutex_unlock(&st->lock); return IRQ_HANDLED; } static irqreturn_t ad7768_interrupt(int irq, void *dev_id) { struct iio_dev *indio_dev = dev_id; struct ad7768_state *st = iio_priv(indio_dev); //printk(KERN_ERR "hank spi test %s %d \n",__FUNCTION__,__LINE__); if (iio_buffer_enabled(indio_dev)) iio_trigger_poll(st->trig); else complete(&st->completion); return IRQ_HANDLED; }; static int ad7768_buffer_postenable(struct iio_dev *indio_dev) { //struct ad7768_state *st = iio_priv(indio_dev); printk(KERN_ERR "hank spi test %s %d \n",__FUNCTION__,__LINE__); /* * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter * continuous read mode. Subsequent data reads do not require an * initial 8-bit write to query the ADC_DATA register. */ //return ad7768_spi_reg_write(st, AD7768_REG_INTERFACE_FORMAT, 0x01); return 0; } static int ad7768_buffer_predisable(struct iio_dev *indio_dev) { struct ad7768_state *st = iio_priv(indio_dev); printk(KERN_ERR "hank spi test %s %d \n",__FUNCTION__,__LINE__); /* * To exit continuous read mode, perform a single read of the ADC_DATA * reg (0x2C), which allows further configuration of the device. */ return ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3); } static const struct iio_buffer_setup_ops ad7768_buffer_ops = { .postenable = &ad7768_buffer_postenable, .predisable = &ad7768_buffer_predisable, }; static const struct iio_trigger_ops ad7768_trigger_ops = { .validate_device = iio_trigger_validate_own_device, }; /* static void ad7768_regulator_disable(void *data) { struct ad7768_state *st = data; regulator_disable(st->vref); } static void ad7768_clk_disable(void *data) { struct ad7768_state *st = data; clk_disable_unprepare(st->mclk); } */ static int ad7768_probe(struct spi_device *spi) { struct ad7768_state *st; struct iio_dev *indio_dev; int ret; //hank test gpio irq int gpio_num; //int irq = 0; struct device_node *test_device_node; //struct property *test_node_property; printk("spi 匹配成功了 \n"); test_device_node = of_find_node_by_path("/spi1"); if (test_device_node == NULL) { printk("spi of_find_node_by_path is error \n"); // return -1; test_device_node = of_find_node_by_name(NULL,"ad7768"); if (test_device_node == NULL) { printk("spi of_find_node_by_name is error \n"); // return -1; } } gpio_num = of_get_named_gpio(test_device_node, "ad7768-sync-in", 0); if (gpio_num < 0) { printk(" spi of_get_named_gpio is error \n"); // return -1; } printk(KERN_ERR "hank spi test %s %d of_get_named_gpio=%d\n",__FUNCTION__,__LINE__,gpio_num); gpio_direction_output(gpio_num,GPIOD_OUT_LOW); //irq = gpio_to_irq(gpio_num); // printk("spi irq is %d \n", irq); //hank test gpio irq printk(KERN_ERR "hank spi test %s %d \n",__FUNCTION__,__LINE__); indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); printk(KERN_ERR "hank spi test %s %d scan_timestamp=%d scan_bytes=%d \n",__FUNCTION__,__LINE__,(int)indio_dev->scan_timestamp,(int)indio_dev->scan_bytes); if (!indio_dev) return -ENOMEM; st = iio_priv(indio_dev); st->spi = spi; /* st->vref = devm_regulator_get(&spi->dev, "vref"); if (IS_ERR(st->vref)) return PTR_ERR(st->vref); ret = regulator_enable(st->vref); if (ret) { dev_err(&spi->dev, "Failed to enable specified vref supply\n"); return ret; } printk(KERN_ERR "hank test %s %d \n",__FUNCTION__,__LINE__); ret = devm_add_action_or_reset(&spi->dev, ad7768_regulator_disable, st); if (ret) return ret; printk(KERN_ERR "hank test %s %d \n",__FUNCTION__,__LINE__); st->mclk = devm_clk_get(&spi->dev, "mclk"); if (IS_ERR(st->mclk)) return PTR_ERR(st->mclk); printk(KERN_ERR "hank test %s %d \n",__FUNCTION__,__LINE__); ret = clk_prepare_enable(st->mclk); if (ret < 0) return ret; printk(KERN_ERR "hank test %s %d \n",__FUNCTION__,__LINE__); ret = devm_add_action_or_reset(&spi->dev, ad7768_clk_disable, st); if (ret) return ret; st->mclk_freq = clk_get_rate(st->mclk); */ st->mclk_freq =16384000; //hank add st->samp_freq =4000; //sampling_frequency_available:1024000 512000 256000 128000 64000 32000 16000 8000 4000 2000 1000 spi_set_drvdata(spi, indio_dev); mutex_init(&st->lock); indio_dev->channels = ad7768_channels; indio_dev->num_channels = ARRAY_SIZE(ad7768_channels); indio_dev->name = spi_get_device_id(spi)->name; indio_dev->info = &ad7768_info; indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_TRIGGERED; indio_dev->scan_timestamp=1; printk(KERN_ERR "hank spi test %s %d scan_timestamp=%d scan_bytes=%d \n",__FUNCTION__,__LINE__,(int)indio_dev->scan_timestamp,(int)indio_dev->scan_bytes); st->gpio_sync_in = gpio_to_desc(gpio_num); if (IS_ERR(st->gpio_sync_in)) { printk(KERN_ERR "hank spi sync_in failed %s %d \n",__FUNCTION__,__LINE__); return PTR_ERR(st->gpio_sync_in); } else printk(KERN_ERR "hank spi sync_in get ok %s %d \n",__FUNCTION__,__LINE__); ret = ad7768_setup(st); if (ret < 0) { dev_err(&spi->dev, "AD7768 setup failed\n"); printk(KERN_ERR "hank spi test %s %d ad7768_setup failed \n",__FUNCTION__,__LINE__); //return ret; } st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d", indio_dev->name, indio_dev->id); if (!st->trig) return -ENOMEM; printk(KERN_ERR "hank spi test %s %d \n",__FUNCTION__,__LINE__); st->trig->ops = &ad7768_trigger_ops; st->trig->dev.parent = &spi->dev; iio_trigger_set_drvdata(st->trig, indio_dev); ret = devm_iio_trigger_register(&spi->dev, st->trig); if (ret) return ret; indio_dev->trig = iio_trigger_get(st->trig); init_completion(&st->completion); printk(KERN_ERR "hank spi test %s %d spi->irq=%d \n",__FUNCTION__,__LINE__,spi->irq); ret = devm_request_irq(&spi->dev, spi->irq, &ad7768_interrupt, IRQF_TRIGGER_RISING | IRQF_ONESHOT, indio_dev->name, indio_dev); if (ret) { printk(KERN_ERR "hank spi test %s %d devm_request_irq failed \n",__FUNCTION__,__LINE__); //return ret; } printk(KERN_ERR "hank spi test %s %d scan_timestamp=%d scan_bytes=%d \n",__FUNCTION__,__LINE__,(int)indio_dev->scan_timestamp,(int)indio_dev->scan_bytes); ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, &iio_pollfunc_store_time, &ad7768_trigger_handler, &ad7768_buffer_ops); if (ret) return ret; return devm_iio_device_register(&spi->dev, indio_dev); } static const struct spi_device_id ad7768_id_table[] = { { "ad7768-1", 0 }, {} }; MODULE_DEVICE_TABLE(spi, ad7768_id_table); static const struct of_device_id ad7768_of_match[] = { { .compatible = "adi,ad7768-1" }, { }, }; MODULE_DEVICE_TABLE(of, ad7768_of_match); static struct spi_driver ad7768_driver = { .driver = { .name = "ad7768-1", .of_match_table = ad7768_of_match, }, .probe = ad7768_probe, .id_table = ad7768_id_table, }; module_spi_driver(ad7768_driver); MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver"); MODULE_LICENSE("GPL v2");

the above is the ad7768-1.c source code,i tried continous reading mode and no continous reading mode,the result is the same

the rk3588-firefly-itx-3588j.dtsi file is:

// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2021 Rockchip Electronics Co., Ltd. * */ #define rk3588 #include "rk3588-firefly-port.dtsi" #include "rk3588-diff.dtsi" / { chosen: chosen { bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0 root=PARTLABEL=rootfs rootfstype=ext4 ro rootwait overlayroot=device:dev=PARTLABEL=userdata,fstype=ext4,mkfs=1 coherent_pool=1m systemd.gpt_auto=0 cgroup_enable=memory swapaccount=1"; }; //ver v1.1 support fan: pwm-fan { compatible = "pwm-fan"; #cooling-cells = ; fan-supply = <&vcc12v_dcin>; pwms = <&pwm15 0 50000 1>; }; }; /* led */ &firefly_leds{ pinctrl-names = "default"; pinctrl-0 =<&leds_gpio>; }; &power_led{ gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; }; &user_led{ gpios = <&pca9555 PCA_IO0_3 GPIO_ACTIVE_HIGH>; }; /* FAN */ &vcc_fan_pwr_en{ status = "okay"; gpio = <&pca9555 PCA_IO1_3 GPIO_ACTIVE_HIGH>; //PCA_IO 13 }; //ver v1.1 support &pwm15 { pinctrl-0 = <&pwm15m2_pins>; status = "okay"; }; /* tf-card */ &sdmmc { status = "okay"; }; &vcc_sdcard_pwr_en{ gpio = <&pca9555 PCA_IO1_5 GPIO_ACTIVE_HIGH>; //PCA_IO 15 status = "okay"; }; &rknpu { status = "disabled"; //hank }; &gpu { status = "disabled"; //hank }; /* can1 */ &can1 { status = "disabled"; //hank: "okay" -->"disabled" for GPIO138, GPIO139 gpio mode assigned-clocks = <&cru CLK_CAN1>; assigned-clock-rates = ; pinctrl-names = "default"; pinctrl-0 = <&can1m1_pins>; }; /* es8323 audio codec */ &i2c3 { status = "disabled"; //hank:status = "disabled"; }; &es8388_sound{ firefly,not-use-dapm; status = "disabled"; //hank:status = "disabled"; }; &es8388{ status = "okay"; }; &i2s0_8ch{ status = "disabled"; //hank:status = "disabled"; }; /* hdmi rx */ &hdmiin_sound{ status = "disabled"; //hank }; &hdmirx_ctrler { status = "disabled"; //hank //hpd-trigger-level = ; //hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; }; /* hdmi0 */ &hdmi0 { //enable-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; status = "disabled"; //hank }; &hdmi0_in_vp0 { status = "disabled"; //hank }; &hdmi0_sound { status = "disabled"; //hank }; &hdptxphy_hdmi0 { status = "disabled"; //hank }; &route_hdmi0{ status = "disabled"; //hank }; /* hdmi1 */ &hdmi1 { enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; status = "disabled"; //hank }; &hdmi1_sound { status = "disabled"; //hank }; &hdmi1_in_vp1 { status = "disabled"; //hank }; &hdptxphy_hdmi1 { status = "disabled"; //hank }; &route_hdmi1{ status = "disabled"; //hank //connect = <&vp1_out_hdmi1>; }; /*ap6275 : bluetooth*/ &wireless_bluetooth{ //status = "okay"; //status = "disabled"; }; &uart6 { pinctrl-names = "default"; pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn>; status = "okay"; }; /* ap6275 : wifi */ &wireless_wlan{ wifi_chip_type = "ap6275p"; pinctrl-0 = <&wifi_poweren_gpio>; /delete-property/ WIFI,host_wake_irq; status = "okay"; }; &combphy1_ps { status = "okay"; }; /* uart/232/485 */ &uart0{ pinctrl-0 = <&uart0m2_xfer>; status = "disabled"; //hank close, pin as irq for AD7768 }; &uart1{ pinctrl-0 = <&uart1m1_xfer>; status = "disabled"; }; /* gamc0 */ &gmac0 { snps,reset-gpio = <&gpio3 RK_PC7 GPIO_ACTIVE_LOW>; tx_delay = ; status = "okay"; }; &gmac0_tx_bus2{ rockchip,pins = /* gmac0_txd0 */ , /* gmac0_txd1 */ , /* gmac0_txen */ ; }; &gmac0_rgmii_bus{ rockchip,pins = /* gmac0_rxd2 */ , /* gmac0_rxd3 */ , /* gmac0_txd2 */ , /* gmac0_txd3 */ ; }; /* gmac1 */ &gmac1 { snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; tx_delay = ; status = "okay"; }; &gmac1_tx_bus2{ rockchip,pins = /* gmac1_txd0 */ , /* gmac1_txd1 */ , /* gmac1_txen */ ; }; &gmac1_rgmii_bus{ rockchip,pins = /* gmac1_rxd2 */ , /* gmac1_rxd3 */ , /* gmac1_txd2 */ , /* gmac1_txd3 */ ; }; /* pcie3.0 x 4 slot */ &pcie30phy { status = "okay"; }; &pcie3x4 { reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; status = "okay"; }; &vcc3v3_pcie30{ gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; startup-delay-us = ; status = "okay"; }; &combphy1_ps { status = "okay"; }; &pcie2x1l0 { //reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; rockchip,skip-scan-in-resume; status = "okay"; }; &combphy2_psu{ status = "okay"; }; &pcie2x1l1{ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; rockchip,skip-scan-in-resume; status = "okay"; }; &combphy0_ps { status = "okay"; }; /* &pcie2x1l2{ reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; rockchip,skip-scan-in-resume; status = "disabled"; }; */ /* sata pm */ &sata0 { status = "okay"; //hank }; &vcc_sata_pwr_en{ status = "okay"; //hank:power don't close, gpio = <&pca9555 PCA_IO1_2 GPIO_ACTIVE_HIGH>; //PCA_IO 12 }; &sata2 { status = "disabled"; //hank }; /* usb power */ &vcc5v0_host{ gpio = <&pca9555 PCA_IO0_5 GPIO_ACTIVE_HIGH>; vin-supply = <&vcc5v0_usb>; status = "okay"; }; &vcc_hub_reset{ status = "okay"; gpio = <&pca9555 PCA_IO0_4 GPIO_ACTIVE_HIGH>; //PCA_IO 04 }; &vcc_hub3_reset{ status = "okay"; gpio = <&pca9555 PCA_IO0_6 GPIO_ACTIVE_HIGH>; //PCA_IO 06 }; &vcc5v0_host3{ gpio = <&pca9555 PCA_IO0_7 GPIO_ACTIVE_HIGH>; //PCA_IO 07 status = "disabled"; }; /* i2c6 */ &i2c6 { clock-frequency = ; // For others Display Port Screen status = "okay"; }; &spi1{ //pinctrl-0 = <&spi1m2_cs0 &spi1m2_cs1 &spi1m2_pins>; //,<&adi_sync_in>; //pinctrl-0 = <&spi1_cs0n &spi1_cs1n &spi1m2_pins>; //hank :gpio-cs //cs-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>,<&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>; //adi,sync_in = <&gpio4 RK_PA4 GPIO_ACTIVE_LOW>; max-freq = ; num-cs = ; /* 配置DMA传输 */ //dmas = <&dmac1 4>; //dma-names = "rx"; //dma-cells = ; status = "okay"; //hank add to open spi1 ad5791: ad5791@1 { compatible = "ad5791"; status = "okay"; //hank change: disabled -->okay , for spi1 demo test reg = ; spi-max-frequency = ; spi-cpha; /* SPI mode: CPHA=1 */ spi-cpol; /* SPI mode: CPOL=1 */ }; ad7768: ad7768@0 { compatible = "ad7768-1"; status = "okay"; //hank change: disabled -->okay , for spi1 demo test reg = ; // need match cs1 -->@1 spi-max-frequency = ; //spi-max-frequency = ; spi-cpha; /* SPI mode: CPHA=1 */ spi-cpol; /* SPI mode: CPOL=1 */ //spi-cs-high; //#interrupt-cells = ; //interrupts = ; //interrupt-parent = <&gpio>; //ad7768-irq-gpio = <&gpio1 RK_PD1 IRQ_TYPE_EDGE_RISING>; /* GPIO1_D1 */ //pinctrl-0 = <&ad7768_irq>; ad7768-sync-in = <&gpio4 RK_PA4 GPIO_ACTIVE_LOW>; /* sync-in */ interrupt-parent = <&gpio4>; interrupts = ; /* 如果硬件支持DMA，则添加DMA通道信息 */ //dma = ; /* 指定DMA通道号 */ }; }; /* pca9555 */ &pca9555{ status = "okay"; //hank:status = "disabled"; }; /* rtc */ &hym8563{ interrupt-parent = <&gpio0>; interrupts = ; status = "okay"; }; /* display port0 */ &spdif_tx2{ status = "disabled"; //hank }; &dp0_sound{ status ="disabled"; //hank }; &dp0 { status = "disabled"; //hank }; &dp0_in_vp2 { status = "disabled"; //hank }; &usbc0{ status = "okay"; interrupt-parent = <&gpio0>; interrupts = ; }; &vbus5v0_typec_pwr_en{ status = "okay"; gpio = <&pca9555 PCA_IO1_4 GPIO_ACTIVE_HIGH>; //PCA_IO 14 }; /* display port1 to vga */ &dp1_in_vp2 { status = "okay"; }; &dp1 { pinctrl-names = "default"; pinctrl-0 = <&dp1_hpd>; hpd-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; status = "okay"; }; &route_dp1{ status ="okay"; //hank connect = <&vp2_out_dp1>; }; /* pinctrl */ &pinctrl { dp { dp1_hpd: dp1-hpd { rockchip,pins = ; }; }; ad7768 { ad7768_irq: ad7768-irq { rockchip,pins = ; }; }; leds { leds_gpio: leds-gpio { /* led_power */ rockchip,pins = ; }; }; hdmirx { hdmirx_det: hdmirx-det { rockchip,pins = ; }; }; headphone { hp_det: hp-det { rockchip,pins = ; }; }; hym8563 { hym8563_int: hym8563-int { rockchip,pins = ; }; }; lcd { lcd_rst_gpio: lcd-rst-gpio { rockchip,pins = ; }; }; touch { touch_gpio: touch-gpio { rockchip,pins = , ; }; }; usb-typec { usbc0_int: usbc0-int { rockchip,pins = ; }; }; wireless-bluetooth { uart6_gpios: uart6-gpios { rockchip,pins = ; }; bt_reset_gpio: bt-reset-gpio { rockchip,pins = ; }; bt_wake_gpio: bt-wake-gpio { rockchip,pins = ; }; bt_irq_gpio: bt-irq-gpio { rockchip,pins = ; }; }; wireless-wlan { wifi_host_wake_irq: wifi-host-wake-irq { rockchip,pins = ; }; wifi_poweren_gpio: wifi-poweren-gpio { rockchip,pins = ; }; }; //hank :gpio-cs spi1 { spi1_cs0n: spi1-cs0n { rockchip,pins = ; }; spi1_cs1n: spi1-cs1n { rockchip,pins = ; }; adi_sync_in: adi-sync-in{ rockchip,pins = ; }; }; }; // for fan when deep sleep &vdd_log_s0{ regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = ; }; }; &avcc_1v8_s0{ regulator-state-mem { regulator-on-in-suspend; }; }; &vcc_1v8_s0{ regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = ; }; }; &rockchip_suspend{ rockchip,sleep-mode-config = < (0 | RKPM_SLP_ARMOFF_DDRPD ) >; };

Could you please look into my case,thank you!